Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-12-27
2004-02-10
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C703S015000
Reexamination Certificate
active
06691288
ABSTRACT:
REFERENCE TO COMPACT DISCS (CD-R'S) FILED WITH THE APPLICATION
Duplicate compact discs (CD-R's) have been filed with the present application. Each compact disc contains a file called “getdata” (48.6 kB, created Oct. 31, 2001) which is an embodiment of the “getdata” script identified herein, and a file called “gencell” (54.5 kB, created Oct. 31, 2001) which is an embodiment of the “gencell” script identified herein. The material on the compact discs is incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention generally relates to the field of ASIC design and software used for debugging simulation results at the gate level, and more specifically relates to a method of efficiently and accurately debugging IKOS models.
IKOS tools provide two basic flows for ASIC design. The first flow is a software-based flow wherein a netlist and test-bench are fed into the software simulator to validate functionality and timing of the design. The second flow is wherein a hardware accelerator is used to read in the synthesized version of the design netlist along with the test-bench for validating the design. This hardware flow increases throughput and hence turn-around times for design validation is markedly reduced compared to the software flow. Third party IKOS models or libraries for the FlexStream release (FS 2.0.2/FS 3.x) are built from their Verilog equivalents. These models are instantiated in a design netlist to model the functionality or timing of the ASIC being, designed.
The typical IKOS model generation and DEBUG process is as follows: a Verilog model is created, an IKOS tool called a “Precision-Verilog to IKOS” or P-VLI reads in the Verilog model to create a .pin, .lde, .dat and .gbl file, all of which together comprise an IKOS model. The .gbl file is common to all cells for a specific technology. Hence, an IKOS model is primarily divided into the following components: a .pin file, a .lde file and a .dat file. Specifically, the functionality of the cell is represented in the .pin file, all the timing information for the cell is contained in the .lde file, and the default timing values for the cell are contained in the .dat file. Of these, the IKOS user mainly deals with the .pin and .lde files to build and validate (i.e. debug) an ASIC design. The .pin and .lde files are written in “Future Net” which is an IKOS proprietary language. This makes the .pin and .lde files very difficult to comprehend and almost impossible to hand-edit. In fact, the files are so complex that they do not effectively convey to a novice user any information about the circuit the file is trying to represent. Hence, debugging a typical IKOS model is relatively difficult and requires that one be very proficient at deciphering .pin and .lde files.
OBJECTS AND SUMMARY
A general object of an embodiment of the present invention is to effectively make the .pin and .lde files of an IKOS model readable and editable so that any functional and timing issues in the model can be efficiently and accurately fixed.
Another object of an embodiment of the present invention is to create an easy to adapt, user-friendly debugging flow for IKOS libraries.
Still another object of an embodiment of the present invention is to reduce turn around time for updates and fixes.
Yet another object of an embodiment of the present invention is to allow a user to better optimize for performance any given IKOS model.
Still yet another object of an embodiment of the present invention is to ensure a 1-to-1 correspondence between Verilog and IKOS views, in terms of model functionality.
Another object of an embodiment of the present invention is to provide a simple, easy to learn methodology which makes cross-training a lot easier.
Another object of an embodiment of the present invention is to incorporate Flexcheck methodology to handle negative timing checks (NTC), which is a FlexStream 3.0 requirement.
Still another object of an embodiment of the present invention is to be able to accommodate both 2.0.2 and 3.x FlexStream versions.
Briefly, and in accordance with at least one of the foregoing objects, an embodiment of the present invention provides a method of debugging an IKOS model, wherein the IKOS model includes a .pin file containing information relating to functionality of a cell, and the IKOS model includes a .lde file containing timing information for the cell. The method includes mapping information contained in either the .pin file, the .lde file or both into corresponding files which are more user-friendly, readable and editable. Preferably, a .v file which is readable to create a schematic view of the cell is also created and the schematic view can be viewed and analyzed. Then, the one or more user-friendly files which have been created can be read and edited, and the .pin and/or the .lde file is re-created. Then, a tool is used to analyze the .pin and .lde files again and determine whether there is a failure.
REFERENCES:
patent: 6240376 (2001-05-01), Raynaud et al.
patent: 6336087 (2002-01-01), Burgun et al.
patent: 6587995 (2003-07-01), Duboc et al.
Marantz, J., “Enhanced visibility and performance in functional verification by reconstruction” Design Automation Conference, 1998. Proceedings, Jun. 15-19, 1998 pp. 164-169.*
Wang et al., Incremental netlist compilation for IKOS hardware logic simulator ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE, Sep. 25-28, 1989 pp. P9-3/1-4.
Fakhry Nader
Gagvani Jayendra P.
Lakshmanan Viswanathan
Liu Andrea
LSI Logic Corporation
Siek Vuthe
Trexler, Bushnell Giangiorgi, Blackstone & Marr, Ltd.
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