Method to create a copper diffusion deterrent interface

Details Method to create a copper diffusion deterrent interface Method to create a copper diffusion deterrent interface

2000-08-10

2004-01-27

Thomas, Tom (Department: 2811)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S624000, C438S637000, C438S639000, C438S666000, C438S672000

Reexamination Certificate

active

06683002

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates generally to an improved ultra large-scale integrated (ULSI) circuit having a copper sulfide interface layer. More particularly, the present invention relates to the fabrication of ULSI using a dual damascene process in conjunction with using a copper sulfide interface layer.
2. Description of Prior Art
The dual damascene process, in which metal is buried inside patterned grooves in a substrate, is frequently used and has become one of the best methods for fabricating USLI circuits. Conventionally, metallic interconnects are formed by depositing a metallic layer over an insulating layer, for example, a silicon dioxide layer. Then, the insulating layer is etched to form a pattern of predefined conductive lines so that a vertical via hole can be formed between conductive layers. Thereafter, metallic material is deposited into the via hole to complete vertical connection between the conductive layers forming an interconnect. Conventionally, there can be a passivation layer formed between the two conductive layers. (See
FIG. 1
,
14
)
Workers in the art are aware that when the passivation layer or any other layer that is positioned on the top of a lower interconnect
12
is etched away from the bottom of the via hole the sputtering of the copper onto the via hole side walls
28
usually occurs. Consequently, copper ions have migrated into the dielectric material, which would result in a change in device properties, and ultimately not being able to use the device. The current invention makes the use of a barrier layer optional thus saving a costly step in production of the devices. Others have striven to solve this problem by lining the via hole with barrier metal layers (See
FIG. 2
,
24
). For Example, U.S. Pat. No. 5,933,758 (Jain) teaches a barrier layer over a dual damascene opening. U.S. Pat. No. 5,693,563 (Teong) shows dual barrier layers in a dual damascene process. U.S. Pat. No. 5,451,542 (Ashby) teaches an S surface passivation process. Even when the barrier layer is used there is still a second problem and that is that these barrier layers usually have thin holes throughout, so that when the copper is deposited in the via hole to form an upper interconnect. The copper diffuses into the dielectric materials, which again would result in a change in device properties, and ultimately not being able to use the device.
Other prior art have shown the use of copper sulfide as a layer. For example, U.S. Pat. Nos. 5,953,628 and 5,863,834 (Kawaguchi and Kawaguchi et al. respectively) teach the use of a copper sulfide on copper wiring. However, the use of copper sulfide is for preventing the oxidation of copper wiring, and it completely surrounds the copper wiring.
SUMMARY OF THE INVENTION
Accordingly, the present invention is to provide a method for forming a dual damascene interconnect structure, wherein migration or diffusing of copper ions into the dielectric material is deterred by depositing a copper sulfide interface layer. Moreover, another objective of the present invention is the cost savings of the barrier layer now being optional.
A method for forming a dual damascene opening by providing a semiconductor structure having a first dielectric layer and a lower interconnect, then forming a passivation layer over the first dielectric layer and forming a stack dielectric layer over the passivation layer. Then patterning and etching the stack dielectric layer to form an upper interconnect opening, and forming an interface layer over the passivation layer, on sidewalls of the upper interconnect opening and on top of the stack dielectric layer. Finally, patterning and etching the passivation layer to open the bottom of the upper interconnect opening and removing the passivation layer from the stack dielectric but not from the sidewalls of the upper interconnect opening.
In the alternative forming the interface layer after the etching and patterning of the passivation layer, and again leaving the interface layers on the sidewalls of the upper interconnect opening after removing some of the interface layer.
The product of a semiconductor structure having a first dielectric layer and a lower interconnect. A passivation layer over the first dielectric layer, and then a stack dielectric layer over the passivation layer. Finally, an upper interconnect opening through the stack dielectric layer and said passivation layer having sidewalls consisting of an interface layer.


REFERENCES:
patent: 5451542 (1995-09-01), Ashby
patent: 5654245 (1997-08-01), Allen
patent: 5693563 (1997-12-01), Teong
patent: 5863834 (1999-01-01), Kawaguchi et al.
patent: 5933758 (1999-08-01), Jain
patent: 5953628 (1999-09-01), Kawaguchi
patent: 6040243 (2000-03-01), Li et al.
patent: 6335570 (2002-01-01), Mori et al.
patent: 10-22285 (1998-01-01), None

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