Method to control paging subsystem processing in virtual memory

Details Method to control paging subsystem processing in virtual memory Method to control paging subsystem processing in virtual memory

1996-10-04

1999-12-21

Teska, Kevin J.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

36422282, 3642543, 3642563, 364DIG1, G06F 900, G06F 1200

Patent

active

RE0364622

ABSTRACT:
A method to logically serialize a plurality of independent system events in a virtual memory data processing system. Each event causes interrupt servicing routines to be executed and requires data structures that record the status of virtual pages to be updated. The system events include the interrupt that is generated as a result of a page fault, the interrupt that is generated as a result of a paging I/O completion operation that resolves a page fault, and lastly interrupts generated in response to a supervisory call to a paging service.

REFERENCES:
patent: 4355360 (1982-10-01), Asano et al.
patent: 4403283 (1983-09-01), Myntti et al.
patent: 4418385 (1983-11-01), Bourez
patent: 4422145 (1983-12-01), Sacco et al.
patent: 4742450 (1988-05-01), Duvall et al.
patent: 4748586 (1988-05-01), Bonci
patent: 4761737 (1988-08-01), Duvall et al.
patent: 4800489 (1989-01-01), Moyer et al.
patent: 4805097 (1989-02-01), De Sanna
patent: 4868738 (1989-09-01), Kish et al.
patent: 4930068 (1990-05-01), Katayose et al.

Affiliated with

Also associated with

Rating

Method to control paging subsystem processing in virtual memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method to control paging subsystem processing in virtual memory , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to control paging subsystem processing in virtual memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-493349