Radiation imagery chemistry: process – composition – or product th – Including control feature responsive to a test or measurement
Reexamination Certificate
1999-11-12
2001-05-22
Young, Christopher G. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Including control feature responsive to a test or measurement
C430S313000, C438S014000, C438S016000, C438S949000
Reexamination Certificate
active
06235440
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the general field of pattern formation through photolithography with particular reference to batch to batch uniformity control.
BACKGROUND OF THE INVENTION
The manufacture of integrated circuits involves laying down many layers of different materials each of which is formed into a different pattern using standard photolithographic techniques. In general, one wafer is processed at a time so that differences in the widths of lines of the actual photoresist patterns will vary somewhat from wafer to wafer. An example of this is illustrated in
FIG. 1
which shows the CD (critical dimension or minimum width) for lines that were fbrmed using the same reticle, or mask, on eight different wafers.
Lines
11
and
12
in
FIG. 1
represent the upper and lower bounds for the CD to fall within the specified limits. In this example, wafers
2
and
6
had a CD that was too high while wafer
7
had a CD that was too low. Variations of this sort are the result of small, but unavoidable, changes that take place during exposure and subsequent processing of the photoresist. These include such factors as the numerical aperture and depth of focus of the optical reduction system as well as the times and temperatures used to develop the photoresist.
The most common approach to dealing with this in the prior art has been to simply strip off the photoresist whenever the CD is found to be out of spec. and then start again. This can be expensive and does not guarantee that the problem will not arise again.
A somewhat more sophisticated approach used in the prior art is to measure the wafers as in their patterns are generated, accepting those that are within spec and then using the out of spec data to adjust the full photolithographic process (numerical aperture, development parameters, etc.). A flow chart representation of this method is shown in FIG.
2
. While this approach reduces the wafer to wafer variations in CD it is not sufficiently reliable to allow removal of the feedback loop once the system appears to have settled down. Additionally, deciding what changes are to be made to the photolithographic process, based on the measured CDs, can be quite complicated and difficult to implement.
Another problem associated with the photolithography of fine lines is that of edge roughness and foot formation. Inevitably the edges of lines formed in photoresist cannot be completely straight and a certain amount of ripple will appear. As lines get to be finer and finer this edge roughness begins to be a significant fraction of the actual line width. In
FIG. 3
a
we show an example of foot formation in a line of photoresist. Line
30
is about 0.16 microns wide and about 0.38 microns high. Foot
31
can be seen extending about 0.015 microns outward at its base. The presence of the foot introduces a level of uncertainty into the width of any line that is subsequently etched using this line of photoresist as a mask. The prior art process discussed above provides no correction for either the roughness problem the line foot problem.
Also used in the prior art is a process whereby the width of the photoresist lines can be reduced by exposing them to a gas plasma discharge. This approach is satisfactory when the measured CD of the photoresist lines is too high (such as for wafers
2
and
6
in FIG.
1
), but cannot be used when the CD is too low (such as for wafer
7
in FIG.
1
). An example of a photoresist line whose foot has been removed through exposure to a gas discharge plasma is shown in
FIG. 3
b.
A routine search of the prior art was conducted but no references teaching the exact method of the present invention were found. Several references of interest were, however, seen. For example, Yang (U.S. Pat. No. 5,913,102) shows a system for controlling CD using a measurement parameter and a control parameter. Yang does not specifically discuss photoresist trimming processes related to CD of gates
Muller et al (U.S. Pat. No. 5,674,409) show a photoresist trimming process that uses ashing while Shinagawa et al. (U.S. Pat. No. 5,057,187) show a method of controlling such an ashing process.
Leung (U.S. Pat. No. 4,717,445) shows an etch bias monitoring technique while Bindell et al. (U.S. Pat. No. 5,804,460) show a method for measuring photoresist line widths.
SUMMARY OF THE INVENTION
It has been an object of the present invention to provide a process for limiting variations in line width of photoresist patterns from wafer to wafer.
Another object of the invention has been to provide a process for reducing edge roughness in photoresist lines.
Still another object of the invention has been to provide a process for removing feet in photoresist lines.
A further object of the invention has been that said process be low cost and suitable for photoresist lines that are both too wide and too narrow.
These objects have been achieved by increasing all line widths in the original pattern data file by a fixed amount that is sufficient to ensure that all lines will be wider than the lowest acceptable CD value. Using a reticle generated from the modified data file, the pattern is formed in photoresist and the resulting CD value is determined. If this turns out be outside (above) the acceptable CD range, the amount of deviation from the ideal CD value is determined and fed into suitable software that calculates the control parameters (usually time) for an ashing routine. After ashing, the lines will have been reduced in width by the amount necessary to obtain the correct CD. A fringe benefit of this trimming process is that edge roughness of the photoresist lines is reduced and line feet are removed.
REFERENCES:
patent: 4717445 (1988-01-01), Leung
patent: 5057187 (1991-10-01), Shinagawa et al.
patent: 5674409 (1997-10-01), Muller
patent: 5804460 (1998-09-01), Bindell et al.
patent: 5913102 (1999-06-01), Yang
Chen Fang-Cheng
Lin Huan-Just
Tao Hun-Jan
Ackerman Stephen B.
Saile George O.
Taiwan Semiconductor Manufacturing Company
Young Christopher G.
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