Method to control dual damascene trench etch profile and...

Details Method to control dual damascene trench etch profile and... Method to control dual damascene trench etch profile and...

2007-07-24

2007-07-24

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S624000, C438S637000, C438S638000, C438S639000, C438S671000, C438S672000, C438S687000, C438S597000, C257SE21555, C257SE21257, C257SE21546, C257SE21259, C257SE21303

Reexamination Certificate

active

10767292

ABSTRACT:
A method of forming trench openings in a dual damascene trench and via etch process by using a two component hard mask layer, termed a bi-layer, over different intermetal dielectrics, IMD, to solve dual damascene patterning problems, such as, fencing and sub-trench formation. Via first patterning in dual damascene processing is one of the major integration schemes for copper backend of line (BEOL) integration. Via first dual damascene scheme usually uses a hard mask layer deposited on top of an inter-metal dielectric (IMD) film stack. The dual damascene trench etch requires uniform trench depth across wafer after etch. In addition, via top corner profiles need to be well maintained without any fencing or faceting. The present method solves these problems by using a two component hard mask layer, termed a bi-layer, deposited directly on top of an inter-metal dielectric (IMD) film stack.

REFERENCES:
patent: 6309962 (2001-10-01), Chen et al.
patent: 6472306 (2002-10-01), Lee et al.
patent: 6603204 (2003-08-01), Gates et al.
patent: 6605874 (2003-08-01), Leu et al.
patent: 2003/0176058 (2003-09-01), Weidman et al.
patent: 2005/0110152 (2005-05-01), Wang et al.
patent: 2005/0186782 (2005-08-01), Burke et al.

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