Method to avoid via poisoning in dual damascene process

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S637000, C438S643000, C438S653000, C438S687000, C438S700000, C438S761000

Reexamination Certificate

active

06800548

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for making semiconductor devices.
2. Background of the Invention
The dual damascene process is widely used in semiconductor device fabrication. As part of fabricating the semiconductor device using the dual damascene fabrication process a conductive layer is formed on a substrate. Next, a barrier layer made from either silicon nitride or silicon carbide is deposited on the conductive layer to act as an etch stop. Shunt metal layers such as cobalt or tungsten may be used as a copper diffusion barrier.
The use of silicon nitride by itself as a barrier layer is undesirable due to its high dielectric constant (k).
The use of silicon carbide by itself as a barrier layer is also undesirable because silicon carbide has organic components and these organic components cause “via poisoning”. As a result, these contaminants cause an undesirably high via resistance. Moreover, Silicon carbide is not a hermetic sealer, allowing undesirable moisture to diffuse through it causing undesirable effects in the semiconductor device.


REFERENCES:
patent: 5045870 (1991-09-01), Lamey et al.
patent: 5187119 (1993-02-01), Cech et al.
patent: 6222269 (2001-04-01), Usami
patent: 6365529 (2002-04-01), Hussein et al.
patent: 6392254 (2002-05-01), Liu et al.
patent: 6448185 (2002-09-01), Andideh et al.
Pllentier, Ivan et al., “Dual Damascene Back-end Patterning Using 248nm and 193nm Lithography”, Semiconductor Fabtech, 13th edition, pp. 227-234.
Hsia, Wei-Jen et al., “Flowfill Technology Low-Dielectric-Constant Materials”, Semiconductor Fabtech, 10th edition, pp. 291-293.
Mills, Michael E. and McClear, Mark, “Integration Challenges of the Low-k Roadmap”, http://www.future-fab.com/documents, Oct. 18, 2001, eight pages.
“Copper, with and without Damascene”, http://www.semiconductors.net/technical/damascene _copper.htm; Oct. 19, 2001, four pages.
“Damascene technology”, http://www.cyberfab.net/training/selfstudy/damascene_technology_1.html; Oct. 19, 2001, eight pages.
Bursky, Dave, “The Wisdom of the Ancients Meets VLSI”, http://www. planetee.com/planetee/servlet; Oct. 19, 2001, two pages.
“Chemical Vapor Deposition (CVD): How Performance Materials Creates High-Performance Silicon Carbide Products”, http://www.performancematerial.com; Oct. 23, 2001, two pages.
“PECVD”, http://ww.ionic.com/PECVD/pecvd.htm Oct. 23, 2001; 2 pages.
Seaward, K.L. and Jezl, M.L., “Using Plasma Energetics to Influence Silicon Nitride Step Coverage”, presented Thursday, Oct. 5, 2000 in Session: Fundamental of Plasma Enhanced Chemical Vapor Deposition; http://www.cae.wisc.edu; one page.

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