Method to avoid copper contamination on the sidewall of a via or

Details Method to avoid copper contamination on the sidewall of a via or Method to avoid copper contamination on the sidewall of a via or

1999-11-15

2000-09-05

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438633, 438638, 438648, 438656, 438666, 438685, 438668, 438669, 438671, 438672, H01L 2144

Patent

active

061142433

ABSTRACT:
A new method to prevent copper contamination of the intermetal dielectric layer during via or dual damascene etching by forming a capping layer over the first copper metallization is described. A first copper metallization is formed in a dielectric layer overlying a semiconductor substrate wherein a barrier metal layer is formed underlying the first copper metallization and overlying the dielectric layer. The first copper metallization is planarized, then etched to form a recess below the surface of the dielectric layer. A conductive capping layer is deposited overlying the first copper metallization within the recess and overlying the dielectric layer. The conductive capping layer is removed except over the first copper metallization within the recess using one of several methods. An intermetal dielectric layer is deposited overlying the dielectric layer and the conductive capping layer overlying the first copper metallization. A via or dual damascene opening is etched through the intermetal dielectric layer to the conductive capping layer wherein the conductive capping layer prevents copper contamination of the intermetal dielectric layer during etching. The via or dual damascene opening is filled with a metal layer to complete electrical connections in the fabrication of an integrated circuit device.

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