Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-02-28
2006-02-28
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S639000, C438S672000, C438S675000, C438S696000, C438S720000, C438S722000, C438S742000
Reexamination Certificate
active
07005375
ABSTRACT:
A process for preventing interconnect metal diffusion into the surrounding dielectric material. Prior to the formation of a metal interconnect in an opening of a dielectric region, the underlying metal surface is cleaned, during which metal can be deposited on the sidewalls of the opening. This metal can diffuse into the dielectric and cause leakage currents. To prevent deposition of the metal onto the sidewalls a barrier layer is deposited into the opening and sputtered onto the sidewalls before the metal surface cleaning step.
REFERENCES:
patent: 5821168 (1998-10-01), Jain
patent: 5985762 (1999-11-01), Geffken et al.
patent: 6114243 (2000-09-01), Gupta et al.
patent: 6177347 (2001-01-01), Liu et al.
patent: 6251789 (2001-06-01), Wilson et al.
patent: 6265313 (2001-07-01), Huang et al.
patent: 6287977 (2001-09-01), Hashim et al.
patent: 6498091 (2002-12-01), Chen et al.
patent: 6521533 (2003-02-01), Morand et al.
patent: 6576982 (2003-06-01), You et al.
patent: 6607977 (2003-08-01), Rozbicki et al.
patent: 2001/0049181 (2001-12-01), Rathi et al.
patent: 2002/0001952 (2002-01-01), Chooi et al.
patent: 2002/0068458 (2002-06-01), Chiang et al.
patent: 2002/0117399 (2002-08-01), Chen et al.
patent: 2002/0142622 (2002-10-01), Iljima et al.
patent: 2002/0162736 (2002-11-01), Ngo et al.
patent: 2003/0116427 (2003-06-01), Ding et al.
patent: 1 233 448 (2002-08-01), None
patent: 1 233 448 (2002-08-01), None
patent: WO 98/52219 (1998-11-01), None
patent: WO 02/39500 (2002-05-01), None
patent: WO 03/048407 (2003-06-01), None
Karthikeyan Subramanian
Merchant Sailesh M.
Agere Systems Inc.
Thomas Toniae M.
Wilczewski Mary
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