Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2007-10-09
2007-10-09
Padmanabhan, Mano (Department: 2189)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S006000, C711S156000, C711S205000
Reexamination Certificate
active
11204321
ABSTRACT:
An instruction is provided to perform clearing of selected address translation buffer entries (TLB entries) associated with a particular address space, such as segments of storage or regions of storage. The buffer entries related to segment table entries or region table entries or ASCE addresses. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.
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Heller Lisa C.
Pfeffer Erwin F.
Plambeck Kenneth E.
Siegel Timothy J.
Campbell John E.
Namazi Mehdi
Padmanabhan Mano
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