Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-08-29
2008-11-04
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S016000
Reexamination Certificate
active
07448008
ABSTRACT:
Automated verification methodology parsing scripts auto generate testbench hardware design language, such as VHDL or Verilog, from the design source VHDL or Verilog. A formal verification model is then built comprising the testbench VHDL and the design under test. The resulting design verification tool then provides proofs and counterexamples for all of the rules, e.g., auto-generated rules, in the testbench.
REFERENCES:
patent: 4264782 (1981-04-01), Konheim et al.
patent: 5831991 (1998-11-01), Miller et al.
patent: 6279146 (2001-08-01), Evans et al.
patent: 6505317 (2003-01-01), Smith et al.
patent: 6553524 (2003-04-01), Das
patent: 6615392 (2003-09-01), Nadeau-Dostie et al.
patent: 6651225 (2003-11-01), Lin et al.
patent: 6883152 (2005-04-01), Bednar et al.
patent: 6938228 (2005-08-01), Zhong
patent: 7028278 (2006-04-01), Jain
patent: 7334203 (2008-02-01), Chan
patent: 2002/0152060 (2002-10-01), Tseng
patent: 2003/0079189 (2003-04-01), Abadir et al.
patent: 2004/0015799 (2004-01-01), Jain
patent: 2004/0153978 (2004-08-01), Xiang et al.
patent: 2006/0075367 (2006-04-01), Chan
patent: 2006/0117274 (2006-06-01), Tseng et al.
patent: 2007/0005323 (2007-01-01), Patzer et al.
patent: 2007/0174805 (2007-07-01), Hsu et al.
patent: 2007/0271536 (2007-11-01), Seawright et al.
patent: 2008/0098339 (2008-04-01), Chan
patent: 2002141414 (2002-05-01), None
Aagaard et al., “Formal Verification Using Parametric Representations of Boolean Constraints”, Proceedings of 36th Design Automation Conference, Jun. 21-25, 1999, pp. 403-407.
Bassemir, “Method to Debug and Temp Fix Around LSSD VLSI Design Errors”, IBM Technical Disclosure Bulletin, Dec. 1987, pp. 19-22.
Bardell et al. “Random Pattern Testability of the Logic Surrounding Memory Arrays” Jul. 1987 IBM Technical Disclosure Bulletin pp. 521-528.
Seigler Adrian E.
Van Huben Gary A.
Augspurger Lynn L.
International Business Machines - Corporation
Jones II Graham S.
Kik Phallaka
LandOfFree
Method, system, and program product for automated... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method, system, and program product for automated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method, system, and program product for automated... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4050983