Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2002-07-24
2004-10-19
Fleming, Fritz M. (Department: 2182)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S052000, C710S003000
Reexamination Certificate
active
06807600
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system, method, and program for memory based data transfer.
2. Description of the Related Art
A local input/output (I/O) bus is a high-speed input/output (I/O) bus used for coupling peripheral devices, such as storage devices, to a computer system. The Peripheral Component Interconnect (PCI) bus and enhancements to the PCI bus, such as the PCI-X bus, are the commonly used I/O buses.
A PCI physical device is a physical device that may be coupled to the PCI bus. Each PCI physical device may incorporate from one to eight separate PCI functions. A PCI function may be a logical device. Each PCI function may include a configuration header that may be configured to control peripheral devices coupled to the PCI bus. The configuration header may include configuration registers, such as base address registers. Six base address registers comprising base address register
0
(BAR
0
), base address register
1
(BAR
1
), base address register
2
(BAP
2
), base address register
3
(BAR
3
), base address register
4
(BAR
4
), base address register
5
(BAR
5
) may be present in the configuration header. Each base address register maybe 32 bits, i.e., a dword. Further details of the PCI bus are described in the publication entitled “PCI Local Bus Specification” by the PCI Special Interest Group (Revision 2.2, Copyright 1992, 1993, 1995, 1998 PCI Special Interest Group), hereinafter referred to as the “PCI Specification.” Further details of the base address registers are described in Chapter 6 of the “PCI Specification.”
A device adapter, such as a host bus adapter (HBA), may act as the interface between the PCI/PCI-X bus and the storage devices. The interface can control the transfer of data from a computer to a storage device and vice versa. Interfaces for storage disks include the Integrated Drive Electronics (IDE) interface (known also as an Advanced Technology Attachment interface i.e., ATA, interface) and the Serial ATA (SATA) interface. Further details of SATA are described in the publication entitled “Serial ATA: High Speed Serialized AT attachment” by the Serial ATA Working Group (Revision 1.0, Copyright 2001). Technologies analogous to IDE/ATA such as the ATA packet interface (ATAPI) are available for CD ROM and DVD drives. The bandwidth and processing capabilities of the interface can substantially affect system performance, system configuration, system compatibility, system upgradability, etc.
Methods of data transfer defined for devices that interface to a PCI/PCI-X bus include “Bus Master IDE” and “Programmed I/O” (PIO). Bus Master IDE utilizes a direct memory access (DMA) engine within the host bus adapter for the transfer of data, thereby reducing the load on the host processor. In PIO based data transfer, the device adapter acts as a slave, accepts read and write requests from an external bus master, such as the host processor or a bus master controller, and satisfies the request by reading or writing from the attached device. In prior art, data may be transferred one, two or four bytes at a time in PIO based data transfer.
In prior art PIO based data transfer mechanisms the device adapter may include a data port. The data port may be located at a byte address in an I/O address space. The I/O address space may be implemented in a manner known in prior art by a base address register in the device adapter's configuration header space. Since the data port is mapped to an address in the I/O address space, while writing data to a storage device, a PCI device can write two bytes of data to the data port at a time. Similarly while reading data the PCI device can read two bytes of data from the data port at a time. Therefore in prior art PCI IDE implementations of the PIO based data transfer, two bytes of data can be transferred at a time, i.e., two bytes of data are allowed per transaction in the PCI IDE PIO mode.
Notwithstanding the use of data transfer in host bus systems in prior art, there is a need for improved techniques for data transfer in host bus systems.
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U.S. patent application Ser. No. 10/205,664, filed Jul. 24, 2002, entitled “Method, System, and Program for Controlling Multiple Storage Devices”, invented by S. Bissessur & D. R. Smith.
Bissessur Sailesh
Smith David R.
Dutta Rabindranath
Fleming Fritz M.
Intel Corporation
Konrad Raynes & Victor LLP
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