Method, system, and program for configuring components on a...

Electrical computers and digital data processing systems: input/ – Input/output data processing – Data transfer specifying

Reexamination Certificate

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Details

C710S035000

Reexamination Certificate

active

06801963

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system, method, and program for configuring components on a bus for input/output operations.
2. Description of the Related Art
FIG. 1
illustrates a prior art storage device architecture, where an external bus master
2
, such as a network adaptor (e.g., a Fibre Channel controller, Ethernet controller, etc.) may access data in one or more disks
4
,
6
through a Serial Advanced Technology Attachment (SATA) controller
8
over a Peripheral Component Interconnect (PCI) bus
10
, which may utilize the Peripheral Component Interconnect (PCI) or PCI-X protocol. In prior art systems, data being transferred between the external bus master
2
and SATA controller
8
first typically flows through a memory controller
12
and memory
14
, such as a Static Dynamic Random Access Memory (SDRAM). For instance, when the external bus master
2
wants to write data to the disks
4
,
6
, the external bus master
2
may transfer the data to the memory
14
. The SATA controller
8
may then read the data sent to the memory
14
in the write request and write the data to disk
4
,
6
. For a read operation, the SATA controller
8
typically transfers requested read data to the memory
14
and the external bus master
2
typically accesses the read data from the memory
14
. The controllers
2
and
8
may include Direct Memory Access (DMA) engines that perform the actual data movement operations therebetween through the memory
14
.
Further, in the PCI-X prior art, the memory buffer
14
enables read and write bursts between an external bus master
2
and a SATA controller
8
, because current SATA controllers must operate as a bus master to handle burst data transfers. Further details of the PCI and PCI-X protocol are described in the publications “PCI Local Bus Specification”, Rev. 2.3 (PCI Special Interest Group, March 2002) and “PCI-X Addendum to the PCI Local Bus Specification”, Rev. 1.0a (PCI Special Interest Group, July 2000).
Using the memory
14
component to buffer data being transferred between the controllers
2
and
8
provides additional latency and delays because of the additional read and write operations involved in using the memory
14
as an intermediary buffer. For these reasons, there is a need in the art for improved techniques for transferring data between controllers in a bus architecture.


REFERENCES:
patent: 5522054 (1996-05-01), Gunlock et al.
patent: 5854894 (1998-12-01), Lancaster et al.
patent: 6070207 (2000-05-01), Bell
patent: 6209042 (2001-03-01), Yanagisawa et al.
patent: 6275876 (2001-08-01), Valk et al.
patent: 6425024 (2002-07-01), Kelley et al.
patent: 0 653 711 (1995-05-01), None
International Search Report, Annex to PCT invitation to pay additional fees (Form PCT/ISA/206), Jan. 9, 2004, for International Application No. PCT/US 03/22941.
PCI Special Interest Group, “PCI-X Addendum to the PCI Local Bus Specification”,PCI Local Bus, Revision 1.0a, Jul. 24, 2000, pp. 1-113.
PCI Special Interest Group, “PCI Local Bus Specification”,PCI Local Bus, Revision 2.3, Mar. 29, 2002, pp. i-xiv, & 1-112.
PCT International Search Report, Jan. 13, 2004, for International Application No. PCT/US 03/22667.
U.S. patent application Serial No. 10/205,662, filed Jul. 24, 2002, entitled “Method, System, and Program for Returning Data to Read Requests Received Over a Bus”, invented by S. Bissessur, M. A. Schmisseur, & D. R. Smith.
U.S. patent application Serial No. 10/205,663, filed Jul. 24, 2002, entitled “Method, System, and Program for Handling Input/Output Commands”, invented by S. Bissessur, R. P. Mackey, M. A. Schmisseur, & D. R. Smith.

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