Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2008-05-06
2008-05-06
Bataille, Pierre (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S137000, C711S203000, C711S205000, C711S207000, C711S209000
Reexamination Certificate
active
07370174
ABSTRACT:
Provided are a method, system, and program for translating virtual addresses of memory locations within pages of different sizes. In one embodiment, a translation entry containing a physical address is stored in a data structure table for each page. Each virtual address includes a page virtual address which identifies the translation entry containing the physical address of the page containing the memory location. The virtual address may be translated to a translation entry index using the size of the page containing the memory location.
REFERENCES:
patent: 4903234 (1990-02-01), Sakuraba et al.
patent: 5214759 (1993-05-01), Yamaoka et al.
patent: 5263142 (1993-11-01), Watkins et al.
patent: 5471618 (1995-11-01), Isfeld
patent: 5479627 (1995-12-01), Khalidi et al.
patent: 5557744 (1996-09-01), Kobayakawa et al.
patent: 5564005 (1996-10-01), Weber et al.
patent: 5566337 (1996-10-01), Symanski et al.
patent: 5784707 (1998-07-01), Khalidi et al.
patent: 6021482 (2000-02-01), Wu et al.
patent: 6549997 (2003-04-01), Kalyanasundharam
patent: 6625715 (2003-09-01), Mathews
patent: 6671791 (2003-12-01), McGrath
patent: 6750870 (2004-06-01), Olarig
patent: 6760783 (2004-07-01), Berry
patent: 6792483 (2004-09-01), Schmidt
patent: 6804631 (2004-10-01), Kelley et al.
patent: 7010633 (2006-03-01), Arndt et al.
patent: 7117339 (2006-10-01), Gurumoorthy et al.
patent: 2001/0037397 (2001-11-01), Boucher et al.
patent: 2002/0152327 (2002-10-01), Kagan et al.
patent: 2003/0065856 (2003-04-01), Kagan et al.
patent: 2004/0017819 (2004-01-01), Kagan et al.
patent: 2004/0027374 (2004-02-01), Cirne et al.
patent: 2004/0103225 (2004-05-01), McAlpine et al.
patent: 2004/0237093 (2004-11-01), Sluiman et al.
patent: 2005/0080928 (2005-04-01), Beverly et al.
patent: 2005/0144402 (2005-06-01), Beverly
patent: 2005/0216597 (2005-09-01), Shah et al.
patent: 2005/0228920 (2005-10-01), Shah et al.
patent: 2005/0228922 (2005-10-01), Tsao et al.
patent: 2006/0004795 (2006-01-01), Shah et al.
patent: 2006/0004941 (2006-01-01), Shah et al.
patent: 2006/0004983 (2006-01-01), Tsao et al.
patent: 2006/0133396 (2006-06-01), Shah et al.
patent: 2006/0136697 (2006-06-01), Tsao et al.
patent: 2006/0235999 (2006-10-01), Shah et al.
Computer System; http://web.archive.org/web/20021031123016/http://webopedia.com/TERM/c/computer—system.html; p. 1; Wednesday, Oct. 31, 2001.
Buonadonna, P., and D. Culler, “Queue Pair IP: A Hybrid Architecture for System Area Networks”, Proceedings of the 29th Annual International Symposium on Computer Architecture, 2002, pp. 247-256.
Correia, P., “Developing a Third Generation I/O Specification”, Intel Developer Update Magazine, Mar. 2002, pp. 1-4.
Culley, P., U. Elzur, R. Recio, & S. Bailer, “Marker PDU Aligned Framing for TCP Specification (Version 1.0),” Release Specification of the RDMA Consortium, Oct. 25, 2002, 32 pp.
Deyring, K. (Ed.), “Serial ATA: High Speed Serialized AT Attachment”, Rev. 1.0, Aug. 29, 2001, 36 pp.
EP Office Action, Feb. 9, 2006, for International Application No. 03 812 441.8-22111.
Hilland, J., P. Culley, J. Pinkerton, & R. Recio, “RDMA Protocol Verbs Specification (Version 1.0),” Release Specification of the RDMA Consortium, Apr. 2003, 243 pp.
Infiniband, “InfiniBand Architecture Specification vol. 1”, Release 1.0, Oct. 24, 2000, Ch. 1-8, pp. 1-195.
Infiniband, “InfiniBand Architecture Specification vol. 1”, Release 1.0, Oct. 24, 2000, Ch. 9-10, pp. 196-445.
Infiniband, “InfiniBand Architecture Specification vol. 1”, Release 1.0, Oct. 24, 2000. Ch. 11-14, pp. 446-669.
Infiniband, “InfiniBand Architecture Specification vol. 1”, Release 1.0, Oct. 24, 2000, Ch. 15-20, pp. 670-880.
Infiniband, “InfiniBand Architecture Specification vol. 2”, Release 1.0, Oct. 24, 2000, Ch. 1-11, pp. 1-319.
Infiniband, “InfiniBand Architecture Specification vol. 2”, Release 1.0, Oct. 24, 2000, Ch. 12-Appendix D, pp. 320-623.
Institute of Electrical and Electronics Engineers, Inc., “IEEE Std. 802.11b-1999”, Sep. 16, 1999, 17 pp.
Institute of Electrical and Electronics Engineers, Inc., “IEEE Std. 802.3- 2002”, Mar. 8, 2002, 33 pp.
Microsoft Corporation, “Interrupt Architecture Enhancements in Microsoft Windows, Codenamed “Longhorn””, Windows Platform Design Notes, © 2003 Microsoft Corporation, 42 pp.
PCI Special Interest Group, “PCI Local Bus Specification Rev. 2.3: PCI Engineering Change Notice—MSI-X”, Jun. 10, 2003, 23 pp.
PCI Special Interest Group, PCI-SIG 2004; web pages including Mar. 20, 2002 news release “PCI-SIG Releases New PCI Version 2.3 Local Bus Specification for Migration to Low-Voltage Designs,” 18 pp. Available from the Internet at <URL: http://www.pcisig.com>.
PCT International Search Report, Aug. 9, 2004, for International Application No. PCT/US03/37254.
Penokie, G.O. (Ed.), “Information Technology- SCSI Controller Commands-2 (SCC-2)”, T10/Project 1225D, Revision 4, Sep. 12, 1997, 24 pp.
Rangarajan, M., A. Bohra, K. Banerjee, E.V. Carrera, and R. Bianchini, “TCP Servers: Offloading TCP Processing in Internet Servers. Design, Implementation, and Performance”, Technical Report, Rutgers University, 2002, pp. 1-14.
RDMA Consortium, “Architectural Specifications for RDMA over TCP/IP”, [online], 2005, [retrieved on Dec. 22, 2005], retrieved from the Internet at <URL: http://www.rdmaconsortium.org/home>.
Recio, R., P. Culley, D. Garcia, & J. Hilland, “An RDMA Protocol Specification (Version 1.0),” Release Specification of the RDMA Consortium, Oct. 2002, 60 pp.
Salzmann, T., and M. Peppel, “GTO Driving Protection Technique with Status Monitoring”, IEEE Transactions on Industry Applications, vol. 24, Issue 1, Part 1, 1998, pp. 115-120. [Abstract].
Shah, H., J. Pinkerton, R. Recio, & P. Culley, “Direct Data Placement over Reliable Transports (Version 1.0),” Release Specification of the RDMA Consortium, Oct. 2002, 35 pp.
Shanley, T. and D. Anderson, (Eds.), “PCI System Architecture,” 4th ed.; TOC pp. v-xlii; Intro. pp. 1-6; Chapter 1 pp. 7-13; Chapter 2 pp. 15-21; 1999.
Stevens, R.W., “UNIX Network Programming”, 1990, pp. 209-210.
US Final Office Action, May 24, 2006, for U.S. Appl. No. 10/815,902.
US First Office Action, Dec. 13, 2005, for U.S. Appl. No. 10/815,902.
US First Office Action, Mar. 10, 2006, for U.S. Appl. No. 10/816,435.
“Virtual Interface Architecture Specification”, Draft Revision 1.0, Dec. 4, 1997, 83 pp.
Wangdee, W. and R. Billinton, “Utilization of Time Varying Event-based Customer Interruption Cost Load Shedding Schemes”, 2004 International Conference on Probabilistic Methods Applied to Power Systems, Sep. 2004, pp. 769-775. [Abstract].
Weber, R., M. Rajagopal, F. Travostino, M. O'Donnell, C. Monia, & M. Merhar, “Fibre Channel (FC) Frame Encapsulation,” Network Working Group, RFC 3643, Dec. 2003, 17 pp.
Arizpe Arturo L.
Tsao Gary Y.
Bataille Pierre
Birkhimer Christopher D
Intel Corporation
Konrad Raynes & Victor LLP
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