Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-11-07
2006-11-07
Whitmore, Stacy A. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07134103
ABSTRACT:
A method, system, and product are disclosed for determining a voltage drop across an entire integrated circuit package. A geometric description of the entire integrated circuit package is determined. The description is subdivided into non-uniform areas. A resistance of each one of the non-uniform areas is determined. A resistive netlist of the entire integrated circuit package is then determined by combining the resistance of each one of the non-uniform areas. The package is then simulated utilizing the netlist to determine the voltage drop across the entire integrated circuit package.
REFERENCES:
patent: 5598348 (1997-01-01), Rusu et al.
patent: 6134513 (2000-10-01), Gopal
patent: 6311147 (2001-10-01), Tuan et al.
patent: 6675139 (2004-01-01), Jetton et al.
patent: 6842727 (2005-01-01), Hayashi
patent: 2003/0057966 (2003-03-01), Shimazaki et al.
Beattie Michael Werner
Devgan Anirudh
Krauter Byron Lee
Zheng Hui
Fay III Theodore D.
International Business Machines - Corporation
Salys Casimer K.
Whitmore Stacy A.
Yee Duke W.
LandOfFree
Method, system, and product for verifying voltage drop... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method, system, and product for verifying voltage drop..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method, system, and product for verifying voltage drop... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3705258