Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-04-26
2005-04-26
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06886147
ABSTRACT:
The present invention is a method, system, and product for optimizing timing in a circuit after layout of the circuit has been completed. The circuit includes at least one variable delay line and includes coupled endpoint devices. The variable delay line includes multiple, different selectable settings. A current setting of the variable delay line is varied from a maximum setting to a minimum setting. A timing accuracy indicator of a combination of the coupled endpoint devices is determined as the variable delay line is varied from its maximum setting to its minimum setting. Thus, multiple timing accuracy indicators are determined where an indicator is determined for and associated with each one of the settings from the maximum setting to the minimum setting. An optimum one of the selectable settings is determined utilizing the timing accuracy indicators, wherein the optimum one of the settings is associated with an optimum one of the multiple timing accuracy indicators.
REFERENCES:
patent: 6038384 (2000-03-01), Ehrler
patent: 6044209 (2000-03-01), Alpert et al.
patent: 6167557 (2000-12-01), Kudva et al.
patent: 6643832 (2003-11-01), Ray et al.
patent: 6701505 (2004-03-01), Srinivasan
Bradfield Travis Alister
Brown Andrew Carl
Johnson Gregory A.
LSI Logic Corporation
Siek Vuthe
Tat Binh
Yee & Associates P.C.
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