Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-04-05
2010-06-01
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
07730368
ABSTRACT:
Methods, systems and devices for testing flash memory dies are disclosed. According to some embodiments, during the post-wafer sort stage of device manufacture, a plurality of flash memory devices, each of which includes a flash controller die and at least one flash memory die associated with a common housing, are subjected to a testing process, for examples, a batch testing process or a mass testing process. During testing, a respective flash controller residing on a respective flash controller die executes at least one test program to test one or more respective flash memory dies of the respective flash device. A testing system including at least 100 of the flash memory devices and a mass-testing board is disclosed. Furthermore, flash memory devices where the flash controller is operative to test one or more of the flash memory dies are disclosed. Exemplary testing includes but is not limited to bad block testing.
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“An overview of flash architectural developments” by Campardo et al. Proceedings of the IEEE Publication Date: Apr. 2003 vol. 91, Issue: 4 on pp. 523-536 ISSN: 0018-9219 INSPEC Accession No. 7651092.
U.S. Appl. No. 11/326,336, filed Jan. 2006, Lasser.
Lasser Menahem
Meir Avraham
Murin Mark
Britt Cynthia
Sandisk IL Ltd.
Toler Law Group
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