Method, system, and computer program product for timing...

Details Method, system, and computer program product for timing... Method, system, and computer program product for timing...

2006-09-14

2009-10-06

Patel, Niketa I (Department: 2181)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output command process

C710S039000, C710S040000, C710S058000

Reexamination Certificate

active

07600049

ABSTRACT:
Operations in a multi-processor, multi-control block environment are timed using timing queues and instruction queues. Upon receipt of a request for a subchannel control block (SCB) to perform an operation that needs to be timed, the SCB is queued on one of multiple timing queues based on an elapsed timeout limit (ETL) of the operation. There is an ETL for each operation, and each one the multiple timing queues is associated with an ETL for completing an operation. The SCB may be placed at the bottom of the timing queue, the timing queue ordered from oldest to youngest which allows for quickly checking large numbers of SCBs without having to check every element queue and without having to dequeuing the elements from this queue. Upon receipt of a request to perform a high-priority operation, the SCB may be queued in a high priority instruction queue. The SCB may remain the timing queue to retain its order and be placed on a high priority instruction queue for retrying an operation. Upon completion of the operation or occurrence of a timeout, the SCB is dequeued. The SCB may be requeued if it was dequeued upon occurrence of a timeout. One or more timing queues may be checked for SCB operation timeouts by one or more SAPs in a round robin fashion.

REFERENCES:
patent: 5491799 (1996-02-01), Kreuzenztein et al.
patent: 6985455 (2006-01-01), Heath et al.
patent: 7143131 (2006-11-01), Soles et al.
patent: 2004/0117791 (2004-06-01), Prasad et al.
patent: 2004/0230979 (2004-11-01), Beecroft et al.
patent: 1570785 (2005-01-01), None

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