Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-03-08
2011-03-08
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S110000, C716S111000, C716S112000, C716S113000, C716S115000, C716S126000
Reexamination Certificate
active
07904861
ABSTRACT:
A method, system, and computer program product for coupled noise timing violation avoidance in detailed routing of an integrated circuit design are provided. The method includes calculating a noise induced timing violation sensitivity (NITVS) metric for nets in the integrated circuit design as a measure of sensitivity to a timing violation relative to a coupled noise delay adder, prioritizing routing isolation as a function of the NITVS metric for each of the nets to avoid coupled noise timing violations, and outputting the routing isolation priority.
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Belaidi Moussadek
Buehler Markus
Curtin James J.
Matheny Adam P.
Meyer Bryan A.
Cantor & Colburn LLP
Dinh Paul
International Business Machines - Corporation
Kinnaman William
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