Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-04-24
2009-08-11
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07574685
ABSTRACT:
An improved method, system, and article of manufacture for reducing via failures is described. In one approach, additional vias or via cuts are inserted into an IC device to increase the number of cuts in a given area. The additional vias or via cuts are inserted until a sufficient via density level has been reached.
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Dong Xiaopeng
Kao William
Noice David C.
Nunn Gary
Seo Inhwan
Cadence Design Systems Inc.
Garbowski Leigh Marie
Vista IP Law Group LLP.
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