Method, system, and apparatus for tracking defective cache...

Details Method, system, and apparatus for tracking defective cache... Method, system, and apparatus for tracking defective cache...

2008-05-27

2008-05-27

Louis-Jacques, Jacques (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S710000, C714S711000, C714S733000, C365S200000, C379S088100

Reexamination Certificate

active

07380180

ABSTRACT:
To facilitate a processor during a reset operation, a linked list of pointers to a list of defective cache lines is created. The good data bits in defective cache lines are used for creating a linked list or other data structure for storing relevant information regarding defective cache lines.

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