Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-05-01
2011-10-18
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S145000, C711SE12008
Reexamination Certificate
active
08041898
ABSTRACT:
The present disclosure provides a method for reducing memory traffic in a distributed memory system. The method may include storing a presence vector in a directory of a memory slice, said presence vector indicating whether a line in local memory has been cached. The method may further include protecting said memory slice from cache coherency violations via a home agent configured to transmit and receive data from said memory slice, said home agent configured to store a copy of said presence vector. The method may also include receiving a request for a block of data from at least one processing node at said home agent and comparing said presence vector with said copy of said presence vector stored in said home agent. The method may additionally include eliminating a write update operation between said home agent and said directory if said presence vector and said copy are equivalent. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
REFERENCES:
patent: 6654858 (2003-11-01), Asher et al.
patent: 7051163 (2006-05-01), Van Doren et al.
patent: 7475321 (2009-01-01), Gurumurthi et al.
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Agarwal Rajat
Mandviwalla Malcolm
Moga Adrian
Bataille Pierre-Michel
Grossman Tucker Perreault & Pfleger PLLC
Intel Corporation
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