Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2005-07-14
2008-09-02
Patel, Nitin C (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S501000, C713S502000
Reexamination Certificate
active
07421609
ABSTRACT:
Systems and methods for circuits which can reduce the average frequency of a clock signal while keeping the maximum frequency of the clock signal are disclosed. Embodiments of these systems and methods may allow for a circuit which receives a clock signal and can output a clock signal with a frequency which is on average some ratio of the frequency of the received clock signal, but still has a maximum frequency which is substantially equal to the frequency of the received clock signal. In one mode of operation, these circuits may output a clock signal substantially identical to a received clock signal, while in another mode of operation these circuits may output a clock signal substantially identical to a received clock during a time interval, thus reducing the average frequency of the output clock signal with respect to the received clock signal while maintaining the maximum frequency of the received clock signal.
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Akui, Satoshi Dynamic Voltage and Frequency Management Low Power Embedded Micro Processor, pp. 64-65, ISSCC Proceedings, 2004.
Kabushiki Kaisha Toshiba
Patel Nitin C
Sprinkle IP Law Group
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