Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2003-11-26
2009-12-22
Chace, Christian P (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S129000, C711S158000, C711S173000, C707S793000
Reexamination Certificate
active
07636810
ABSTRACT:
In one embodiment, a system includes a main memory including a compression cache to store uncompressed data, where the compression cache is organized as a sectored cache having on-die associated tags. On a tag match to an associated tag, a hit signal is sent to a memory controller coupled to the main memory to schedule an uncompressed data access from the compression cache. A compressed memory may be present to store a plurality of compressed data. Also, a higher priority may be assigned to read operations of the compressed memory in comparison to other operations to the compressed memory. Other embodiments are described and claimed.
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PCT International Search Report and Written Opinion from International Application No. PCT/US2004/037824, date of mailing Mar. 31, 2005, 12 pgs.
Bradley Matthew
Chace Christian P
Intel Corporation
Trop Pruner & Hu P.C.
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