Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-12-25
2007-12-25
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
10787326
ABSTRACT:
A method (600) of designing a programmable logic device can include the steps of identifying a cost function that penalizes floorplans of a circuit design that do not fit on the programmable logic device (605) and defining modules having components of a same type (615). A set of shapes associated with a module can be determined (610). The circuit design can be annealed (620) to determine a floorplan using the cost function and the set of shapes for the module.
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S. Kirkpatrick et al.; “Optimization by Simulated Annealing”; Science; vol. 220, No. 4598; May 13, 1983; pp. 671-680.
Dieter Jungnickel;Graphs, Networks and Algorithms; “Algorithms and Computation in Mathematics”; Chapter 13—Weighted Matchings; vol. 5; Copyright 1999; published by Springer-Verlag Berlin Heidelberg New York; pp. 389-401.
Aggarwal Rajat
Dasasathyan Srinivasan
Saunders James L.
Stenz Guenter
Cuenot Kevin T.
Meles Pablo
Siek Vuthe
Xilinx , Inc.
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