Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-01-31
2006-01-31
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S738000, C714S005110
Reexamination Certificate
active
06993692
ABSTRACT:
An integrated circuit includes a plurality of separate memory arrays each having a respective one of a plurality of inputs and a respective one of a plurality of outputs. Each output provides an output value indicative of whether a storage location associated with an applied address is passing or failing. The integrated circuit further includes a shared built-in self-test (BIST) and repair system coupled to all of the plurality of inputs and all of the plurality of outputs. The shared BIST and repair system applies addresses and data to the plurality of inputs to test the plurality of memory arrays for failing storage locations. In response to detection of a failing storage location in any of the plurality of memory arrays, the shared BIST and repair system applies a common address remapping to all of the plurality of memory arrays to remap, in each memory array, the address associated with the failing storage location to a different storage location
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Ouellette Michael R.
Tellez Gustavo Enrique
Zuchowski Paul Steven
Dillon & Yudell LLP
Tu Christine T.
Walsh Robert A.
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