Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-10-20
2009-02-24
Abraham, Esaw T (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S753000, C714S765000, C714S784000
Reexamination Certificate
active
07496826
ABSTRACT:
A circuit and method for generating an Error Correcting Code (ECC) based on an adjacent symbol codeword that is formed in two clock phases among other techniques are described. In one embodiment, an apparatus is to comprise one or more logics to: generate a plurality of check bits based on a set of data, receive a codeword from a memory and to generate a syndrome based on the codeword, and to detect whether an error exists based on the syndrome. In another embodiment, a logic may classify the error if it exists. In a further embodiment, a logic may correct the error if it exists. Other embodiments are also disclosed.
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Abraham Esaw T
Caven & Aghevli LLC
Intel Corporation
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