Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-05-19
2003-06-17
Auve, Glenn A. (Department: 2189)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S031000, C370S351000, C370S392000, C709S239000, C709S242000
Reexamination Certificate
active
06581126
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of computer busses.
2. Background
A major issue in the information age is the speed at which data can be transferred between points. This issue exists in computers both for transferring data between memory and a central processing unit, and for transferring data between devices and/or memory. The issue also exists for transferring data between computers or digitized voice data between telephone units.
As processor speed and network traffic has increased, the physical limitations of traditional interconnects have become more apparent. With commonly available home computers operating at a clock speed of more than 500 MHz, the computing bottleneck is generally a result of moving data within the system and not as a result of processing the data. Rambuss technology is one approach that addresses a similar problem in providing a high bandwidth interconnection between a processor and memory. Other approaches exist for generalized high speed interconnects such as the scaleable coherent interface (SCI).
One problem is that vast amounts of data need to be transported from one place to another as quickly as possible with minimal latency and maximum throughput.
Another problem in the known art is within multiple processor systems that require copies of the same data in multiple caches. Existing cache-coherency protocols on single-bus multiprocessor systems are limited by the physics of the single bus. That is some of the desirable bus characteristics are incompatible: high bandwidth, low latency, and unlimited length. Thus, increasing the number of processors accessing the bus increases the memory/processor traffic, increases the time required to arbitrate the bus, and physically lengthens the bus (thus decreasing the maximum rate at which it can be clocked, and therefore decreasing the bus' bandwidth).
Single bus multiprocessor systems generally use snooping protocols to maintain cache coherency. The caches on these systems monitor “snoop” bus transactions from other caches to determine whether the transaction affects the cache's contents (effectively, each bus transaction is broadcast to every cache). Replacing the single bus with a point-to-point interconnection to avoid the single bus limitations also removes the broadcast mechanism that is used by the snooping protocols. Thus, the snooping protocols have been considered as not economically feasible for large multiprocessor designs.
It would be advantageous to provide a high speed, highly pipelined, interconnect between one or more processors, caches and memories that supports multi-gigahertz clock rates and four or more times the number of cache agents as is currently supported by known system busses that snoop bus transactions.
SUMMARY OF THE INVENTION
The invention discloses methods and apparatus for broadcasting information across an interconnect that includes a plurality of nodes each connected to its adjacent node(s) using one or more links. The nodes can emit cells containing transaction sub-actions onto the links. As a node receives a cell the node retransmits the cell onto other links as the cell is being received. Thus, reducing the latency imposed by the node. The node also captures the transaction sub-action while it retransmits the cell. The node responds to the transaction sub-action by manipulating shared handshake lines that are bussed with the other nodes. The invention enables snooping cache protocols to be successfully used in a larger multi-processor computer system than the prior art.
The foregoing and many other aspects of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments that are illustrated in the various drawing figures.
REFERENCES:
patent: 4727370 (1988-02-01), Shih
patent: 4736393 (1988-04-01), Grimes et al.
patent: 4845709 (1989-07-01), Matsumoto et al.
patent: 4866706 (1989-09-01), Christophersen et al.
patent: 4882704 (1989-11-01), Komori et al.
patent: 4939752 (1990-07-01), Literati et al.
patent: 4954983 (1990-09-01), Klingman
patent: 5155843 (1992-10-01), Stamm et al.
patent: 5241543 (1993-08-01), Amada et al.
patent: 5410723 (1995-04-01), Schmidt et al.
patent: 5465251 (1995-11-01), Judd et al.
patent: 5734685 (1998-03-01), Bedell et al.
patent: 5764924 (1998-06-01), Hong
patent: 5826037 (1998-10-01), Stiegler et al.
patent: 5828670 (1998-10-01), Narasimha et al.
patent: 5841989 (1998-11-01), James et al.
patent: 5897656 (1999-04-01), Vogt et al.
patent: 5920267 (1999-07-01), Tattersall et al.
patent: 5964845 (1999-10-01), Braun et al.
Efficient broadcast using selective flooding; Arunkumar, S.; Panwar, R.S.; Infocom '92. Eleventh Annual Joint Conference of the IEEE Computer and Communications Societies. IEEE, May 4-8, 1992 pp.: 2060-2067 vol. 3.*
A new flooding routing algorithm based on ‘node-step’ concept ; Sheng-Lin; Jing-Sheng Liu; Singapore ICCS/ISITA '92. ‘Communications on the Move’ , Nov. 16-20, 1992 pp.: 1396-1399 vol. 3.*
Towards a self-healing intelligent network; May, C.J.; Dighe, R.S.; Communications, 1991. ICC 91, Conference Record. IEEE International Conference on, Jun. 23-26, 1991 pp.: 655 -659 vol. 2.*
Master Thesis by Ivan Tving, Aug. 28, 1994, “Multiprocessor interconnection using SCI”.
PCI Local Bus Specification, Revision 2.1, Jun. 1, 1995, PCI Special Interest Group.
PCT To PCI Bridge Architecture Specification, Version 1.0, 1994, PCI Special Interest Group.
Cache Coherence Protocols for Large-Scale Multiprocessors, by David Lars Chaiken.
Auve Glenn A.
PLX Technology, Inc.
Swernofsky Law Group PC
Vu Trisha
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