Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-10-07
2001-02-13
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S653000, C438S663000, C438S680000, C438S681000, C438S687000, C438S611000, C438S612000, C438S613000, C438S614000
Reexamination Certificate
active
06187680
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to packaging of integrated circuits and, in particular, to a method for creating an aluminum (Al) contact which is in electrical communication with the copper (Cu) interconnect wiring of an integrated circuit (IC) device. In one embodiment of the present invention, an aluminum “plug” structure that covers a large via and an underlying copper pad is employed. The second embodiment consists of an aluminum bond pad where the opening to the underlying copper is displaced laterally from the active region of the bond pad and the region defining the copper-aluminum connection is shrunken in size in order to minimize the copper-aluminum via area. The purpose of the aluminum contact that is described in this invention is to cover the exposed copper to prevent environmental attack and/or mixing of the materials used in forming the bond (i.e. lead-tin) with the underlying copper.
BACKGROUND OF THE INVENTION
In semiconductor manufacturing, a fabricated integrated circuit (IC) device is usually assembled into a package to be utilized on a printed circuit board as part of a larger circuit. In order for the leads of the package to make electrical contact with the bonding pads of the fabricated IC device, the metal bond is formed to make a connection between the bonding pad of the IC device and a lead extending to the package lead frame, or a solder ball connection to a ceramic or polymeric chip carrier.
In the past, Al and Al alloys have been used as conventional chip wiring materials. Al wiring material is being replaced by Cu and Cu alloys since Cu wiring provides improved chip performance and superior reliability when compared to Al and alloys of Al. The packaging of IC devices employing copper wiring presents a number of technical issues related to the reaction of copper with material used in the solder-ball process and/or susceptibility of copper to environmental attack and corrosion.
A typical prior art fabricated IC structure before interconnecting with a package is shown in FIG.
1
. Specifically, the fabricated prior art IC structure shown in
FIG. 1
comprises a semiconductor wafer
10
having at least one Cu wiring region
12
embedded in its surface. It is noted that semiconductor wafer
10
includes a plurality of IC device regions therein. For clarity, these IC device regions are not shown in the drawing. The prior art IC structure of
FIG. 1
further includes a passivating layer
14
formed on the surface of semiconductor wafer
10
having an opening therein extending over regions of Cu wiring
12
. In the opening, there is shown a terminal via barrier layer
16
which also extends over portions of the passivating layer near the opening. A second passivating layer
18
typically composed of an organic material such as a polyimide film having an opening over Cu wiring
12
is located on the surface of passivating layer
14
.
The prior art structure shown in
FIG. 1
is normally fabricated by providing a planarized IC wafer containing Cu wiring therein; forming a passivating layer on the surface of the planarized IC wafer; reactive ion etching (RIE) the passivating layer to form terminal via openings over the underlying Cu wiring; providing a barrier layer to said terminal via opening; forming an organic passivating layer on the surface of the barrier layer; and then etching the outer passivating layer to provide an opening to the Cu wiring.
In current practice, large (90 &mgr;m) terminal via openings are formed in passivating layer
14
to expose pads that are created at the underlying Cu wiring level. This process that is utilized in the prior art for Cu back-of-the-line (BEOL) structures was developed from previous BEOL technology wherein wirebond connections are made directly through the terminal via openings to the underlying Cu wiring. For current applications where additional Cu wiring levels are being employed, there are several problems with using the above technology.
First, since copper does not form a self-passivating oxide layer as does aluminum, copper exposed to atmospheric conditions will corrode to a depth of several thousand angstroms degrading the reliability of the IC device. Second, for the solder-ball application, the commonly used ball-limiting or barrier metallurgies may not be compatible with copper metallization and might allow the mixing of the leadtin (Pb—Sn) solder material with the underlying copper. In this event, brittle Cu-Sn intermetallics will form increasing the electrical resistivity and compromising the reliability of the interconnection scheme.
In view of the drawbacks mentioned with the prior art process of a packaging connection on copper wiring IC structures, there is a continued need to develop new and improved processes that overcome the disadvantages associated with prior art processes. The requirements of this structure and method are that it be compatible with conventional chip packaging and test methodologies and that it protect the copper wiring from environmental attack and/or reactions with the packaging materials.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a process for fabricating an Al contact, i.e. bond pad, on Cu BEOL which overcomes all of the problems associated with the prior art method of fabricating the same.
A further object of the present invention is to provide a process for fabricating an Al contact which is in electrical communication with the underlying Cu wiring embedded in an IC structure.
Another object of the present invention is to provide a process for fabricating an Al contact in Cu BEOL structures such that when bonded with a semiconductor package no fracturing of the underlying material layers is observed.
An additional object of the present invention is to provide a process for forming a solder ball connection that would prevent mixing of the solder materials with the copper wiring and would allow utilization of conventionally used solder and ball limiting metallurgy (BLM) materials with the copper interconnect processes.
These and other aspects and advantages can be achieved in the present invention by utilizing a method which comprises the steps of:
(a) forming a passivating layer on an integrated circuit (IC) semiconductor wafer containing Cu wiring therein;
(b) forming terminal via openings through said passivating layer to expose said Cu wiring;
(c) forming a barrier layer at least over said exposed Cu wiring, on the side walls of said terminal via openings and on regions of said barrier layer near said terminal via openings;
(d) forming an Al stack on said barrier layer at least in said terminal via openings and on regions of the barrier layer near said terminal via openings;
(e) patterning and etching said Al stack and said barrier layer;
(f) forming a second passivating layer over said patterned Al stack; and
(g) providing second openings in said second passivating layer so as to expose a region of said patterned Al stack located on top of said Cu wiring.
In one embodiment of the present invention, step (g) above is replaced with (g′), which comprises providing second openings in said second passivating layer so as to expose a region of said patterned Al stack not located on top of said Cu wiring.
In another embodiment of the present invention, the method of the present invention comprises first conducting steps (a)-(g) or (a)-(g′) mentioned above and then providing a wirebond or C4 solder material to said exposed Al stack, i.e. the Al pads, so as to provide means for interconnecting the IC structure to a semiconductor package.
In another aspect of the present invention, an IC structure containing an Al contact in electrical communication with underlying Cu wiring is provided. Specifically, the IC structure of the present invention comprises a semiconductor wafer having Cu wiring embedded therein, a first passivating layer on top of said semiconductor wafer having terminal via openings therein so as to expose said Cu wiring; a barrier layer on at least said exposed Cu wiring, sidewalls of the termin
Costrini Gregory
Goldblatt Ronald Dean
Heidenreich, III John Edward
McDevitt Thomas Leddy
Berry Renee R.
International Business Machines - Corporation
Nelms David
Scully Scott Murphy & Presser
Shkurko, Esq. Eugene I.
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