Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
Reexamination Certificate
2005-01-11
2005-01-11
Ellis, Richard L. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Context preserving (e.g., context swapping, checkpointing,...
C326S039000
Reexamination Certificate
active
06842854
ABSTRACT:
To provide a method of implementing cache logic technique in which total data processing time can be reduced, input data divided into block is sequentially processed in units of block in plural circuits using a programmable logic device provided with a circuit information input controller, a programmable logic circuit sector and a data cache. The plural circuits are sequentially reconfigured in the programmable logic device and execute processing per plural blocks which can be stored in the data cache. Intermediate data in units of plural blocks is stored in the data cache to be input data to a reconfigured circuit and intermediate data as the result of the processing by the reconfigured circuit is overwritten to the data cache. When the processing of the plural circuits is finished, the result of the processing is output to an external device without being stored in the data cache.
REFERENCES:
patent: 5801547 (1998-09-01), Kean
patent: 5844422 (1998-12-01), Trimberger et al.
patent: 6091263 (2000-07-01), New et al.
patent: 6507211 (2003-01-01), Schultz et al.
patent: 6553479 (2003-04-01), Mirsky et al.
patent: 2-130023 (1990-05-01), None
patent: 10-78932 (1998-03-01), None
S. Trimberger et al., “A Time-Multiplexed FPGA”, Proceedings of FPGAs for Custom Computing Machines in 1997 (FCCM 97), pp. 22-28.
E. Tau, et al., “A First Generation DPGA Implementation”, FPD ′95—Third Canadian Workshop of Field Programmable Devices May 29-Jun. 1, 1995.
M. Motomura, et al., “An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration”, 1997 Symposium on VLSI Circuits Digest of Technical Papers, pp. 55-56.
T. Fujii, et al., “A Dynamically Reconfigurable Logic Engine with a Multi-Context/Multi-Mode Unified Cell Architecture”, Digest of Technical Papers, 1999 IEEE International Solid-State Circuits Conference.
Nishihara Yoshio
Sato Yoshihide
Satonaga Tetsuichi
Yamada Norikazu
Ellis Richard L.
Fuji 'Xerox Co., Ltd.
Morgan & Lewis & Bockius, LLP
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