Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle
Reexamination Certificate
2008-12-19
2011-11-15
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
C716S055000, C430S005000
Reexamination Certificate
active
08060842
ABSTRACT:
A method of decomposing a target pattern having features to be imaged on a substrate so as to allow said features to be imaged in a multi-exposure process. The method includes the steps of: (a) segmenting a plurality of the features into a plurality of polygons; (b) determining the image log slope (ILS) value for each of the plurality of polygons; (c) determining the polygon having the minimum ILS value, and defining a mask containing the polygon; (d) convolving the mask defined in step (c) with an eigen function of a transmission cross coefficient so as to generate an interference map, where the transmission cross coefficient defines the illumination system to be utilized to image the target pattern; and (e) assigning a phase to the polygon based on the value of the interference map at a location corresponding to the polygon, where the phase defines which exposure in said multiexposure process the polygon is assigned.
REFERENCES:
patent: 4894790 (1990-01-01), Yotsuya et al.
patent: 5097138 (1992-03-01), Wakabayashi et al.
patent: 5307296 (1994-04-01), Uchida et al.
patent: 5307421 (1994-04-01), Darboux et al.
patent: 5319564 (1994-06-01), Smayling et al.
patent: 5416729 (1995-05-01), Leon et al.
patent: 5536603 (1996-07-01), Tsuchiya et al.
patent: 5621652 (1997-04-01), Eakin
patent: 5795688 (1998-08-01), Burdorf et al.
patent: 5825647 (1998-10-01), Tsudaka
patent: 5966312 (1999-10-01), Chen
patent: 5969441 (1999-10-01), Loopstra et al.
patent: 6046792 (2000-04-01), Van Der Werf et al.
patent: 6081659 (2000-06-01), Garza et al.
patent: 6289499 (2001-09-01), Rieger et al.
patent: 6355382 (2002-03-01), Yasuzato et al.
patent: 6492066 (2002-12-01), Capodieci et al.
patent: 6816233 (2004-11-01), Sugita
patent: 7065738 (2006-06-01), Kim
patent: 7083879 (2006-08-01), Pierrat et al.
patent: 7155689 (2006-12-01), Pierrat et al.
patent: 7398508 (2008-07-01), Shi et al.
patent: 2002/0046392 (2002-04-01), Ludwig et al.
patent: 2003/0118917 (2003-06-01), Zhang et al.
patent: 2003/0126581 (2003-07-01), Pang et al.
patent: 2004/0123265 (2004-06-01), Andreev et al.
patent: 2004/0209170 (2004-10-01), Broeke et al.
patent: 2004/0265707 (2004-12-01), Socha
patent: 2005/0044513 (2005-02-01), Robles et al.
patent: 2005/0122494 (2005-06-01), Kuchibhotla et al.
patent: 2005/0142449 (2005-06-01), Shi et al.
patent: 2005/0149902 (2005-07-01), Shi et al.
patent: 2005/0195379 (2005-09-01), Stanton et al.
patent: 2005/0210437 (2005-09-01), Shi et al.
patent: 2005/0268256 (2005-12-01), Tsai et al.
patent: 2006/0154151 (2006-07-01), Anderson et al.
patent: 2007/0031745 (2007-02-01), Ye et al.
patent: 2009/0053621 (2009-02-01), Socha
patent: 1329771 (2003-07-01), None
patent: 1439420 (2004-07-01), None
patent: 1465016 (2004-10-01), None
patent: 1538484 (2005-06-01), None
patent: 2004221594 (2004-08-01), None
patent: 2004-312027 (2004-11-01), None
patent: 20043122027 (2004-11-01), None
patent: 2005276852 (2005-10-01), None
Barouch, E., et al., “Modeling Process Latitude in UV Projection Lithography”, vol. 12, No. 12, Oct. 1991.
Cobb, N., et al., “Mathematical and CAD Framework for Proximity Correction”, Optical Microlithography IX, Santa Clara, CA Mar. 13-15, 1996, vol. 2726, pp. 208-222.
Crisalle, OD, et al., “A Comparison of the Optical Projection Lithogrpahy Simulators in Samples and Prolith”, IEEE Translactions on Semiconductor MA, vol. 5, No. 1, Feb. 1992.
Gopalaro, K., et al., “An Integrated Technology CAD System for Process and Device Designers”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, No. 4, Dec. 1993.
Mack, C., et al., “Metrology Inspection and Process Control” for Microlithography XV, Santa Clara, CA, Feb. 26, 2001-Mar. 1, 2001, vol. 4344, pp. 377-384.
Neubauer, et al., “Imaging in VLSI Cross Sections by Atomic Force Microscopy”, CH3084-1/92/000-0299$01.00@1992IEEE/IRPS.
Peters, L., “AFMs: What Will Their Role Be?”, 62 / Semiconductor International, Aug. 1993.
Qian, QE, et al., “A New Scalar Planewave Model for High NA Lithography Simulations”, TH0640-3/94/000-0045 $3.00 @ 1994 IEEE.
Randall, J., et al., “Variable Threshold Resist Models for Lithography Simulation”, XP008001832, PD, Mar. 17, 1999, pp. 176-182.
Rodgers, M., “Application of the Atomic Force Microscope to Integrated Circuit Reliablity and Failure Analysis”, CH2974-4/91/000-0250$0.100@1991 IEEE/IRPS.
Yeung, et al., “Extension of the Hopkins Theory of Partially Coherent Imaging to Include Thin Film Interference Effects”, 452/SPIE, vol. 1927, Optical/Laser Microlithography VI (1993).
Search Report issued by Austrian Patent Office in corresponding Singapore matter.
ASML Masktools B.V.
Dimyan Magid
Do Thuan
Pillsbury Winthrop Shaw & Pittman LLP
LandOfFree
Method, program product and apparatus for model based... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method, program product and apparatus for model based..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method, program product and apparatus for model based... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4291608