Static information storage and retrieval – Read/write circuit
Patent
1993-12-06
1995-05-23
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
365184, 365185, 365218, 365168, G11C 1140
Patent
active
054187435
ABSTRACT:
A method of using a non-volatile semiconductor memory comprising a plurality of row and column lines, a plurality of memory cells disposed at intersections of the row and column lines and a plurality of reference cells disposed on each of the row lines. Each memory cell includes an MOS transistor having a substrate, a spaced-apart drain and source formed on one surface of the substrate, a channel region between the drain and source and a lamination of a tunnel insulating film, a floating gate, an interlayer insulating film and a control gate formed in that order on the channel region. Each reference cell has the same electrical characteristic as the memory cell, with the method including:
REFERENCES:
patent: 4964079 (1990-10-01), Devin
patent: 5068827 (1991-11-01), Yamada et al.
Y. Tokioka, Y. Sato, S. Iwasa, K. Anzai, and T. Wada, "The Proposal of Multi-Bit Type Flash Memory", The 53rd Autumn Meeting, 1992, The Japan Society of Applied Physics, No. 2, 17a-ZS-9.
Anzai Kenji
Iwasa Shoichi
Sato Yasuo
Tomioka Yugo
Wada Toshio
Nippon Steel Corporation
Niranjan F.
Popek Joseph A.
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