Method of writing ferroelectric field effect transistor

Details Method of writing ferroelectric field effect transistor Method of writing ferroelectric field effect transistor

2002-05-01

2004-07-06

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S065000

Reexamination Certificate

active

06760246

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuit transistors, and in particular to a ferroelectric field effect transistor (FET).
BACKGROUND OF THE INVENTION
Ferroelectric nonvolatile random access memory devices preserve the stored data state, even when the power supply signal is removed. The logic state of each memory cell generally is based on the electrical polarization of a ferroelectric capacitor, including a ferroelectric material sandwiched between two conductive or semi-conductive layers. When an electric field of sufficient magnitude is applied across the ferroelectric capacitor, the ferroelectric material will polarize in the direction of that electric field. The minimum voltage that must be applied across the capacitor in to order to initiate reversal of the polarization state is defined as the coercive voltage.
It is well known that direction of the polarization may be sensed by applying a voltage greater than the coercive voltage across a ferroelectric capacitor, and sensing the resulting current flow. If the polarity of the voltage applied is opposite to the polarization in a ferroelectric capacitor, the polarization of the ferroelectric capacitor will switch to the opposite state. If, on the other hand, the polarization in the ferroelectric capacitor is the same as the voltage applied, the ferroelectric capacitor will not switch polarization states. Since significantly more current results when a polarization switch occurs than when it does not, the resulting current can be used to determine the logic state of the ferroelectric capacitor. When reading is complete, the cells must be rewritten to their original logic states. This method is referred to as a “destructive read-out” since the data stored in the ferroelectric capacitor is temporarily overwritten.
Also known in the art are various “non-destructive read-out” sensing techniques wherein the polarization stored in the ferroelectric capacitor is sensed without disturbing or destroying the stored polarization state. Such methods are generally based on detecting the capacitance of the ferroelectric capacitor by applying voltages less than the coercive voltage across the terminals of the ferroelectric capacitor.
Ferroelectric memory cells based on sensing the state of polarization of a ferroelectric capacitor, whether sensed destructively or non-destructively, result in a memory cell that requires additional transistor devices for selection of a particular cell within the memory array. Ferroelectric memories based on a class of devices known as ferroelectric field effect transistors (FETs) could offer significant memory cell size advantages, thereby decreasing the manufacturing cost dramatically. A ferroelectric FET known in the prior art is structurally identical to a metal-oxide-silicon field effect transistor (MOSFET) device with the oxide replaced by a ferroelectric material, as shown in FIG.
1
. The structure is constructed on p-type semiconductor substrate
10
with two regions of n-type regions forming source
12
and drain
14
. Channel region
16
is disposed in the region between source
12
and drain
14
. A ferroelectric layer
18
is formed on the surface of channel region
16
. A conductive layer formed on the surface of ferroelectric
18
forms gate electrode
20
.
In operation, a logic state is written into the ferroelectric FET by applying a voltage greater than the coercive voltage across the ferroelectric layer, thereby setting the state of polarization of that ferroelectric layer. After the write voltages are removed, the state of polarization of the ferroelectric layer gives rise to an electric field, which shifts the turn-on threshold voltage level of the ferroelectric FET. This principle is utilized to retrieve the logic state from the ferroelectric FET.
FIG. 2
illustrates one example of a voltage bias applied to source
12
, drain
14
, gate electrode
18
and substrate
10
in order to produce a polarization within the ferroelectric layer
18
corresponding to a first logic state as is known in the prior art. In this example, −3v is applied to gate electrode
20
, and 0v is applied to source
12
, drain
14
, and substrate
16
. Positive charges are attracted to channel
16
putting this device in “accumulation mode”, thereby creating a potential in channel region
16
equal to the substrate voltage, which is biased to 0v. Assuming that the coercive voltage is 3v or less, the electric field thereby created across the ferroelectric will polarize the ferroelectric layer in the direction of that electric field. This electric field will have the effect of increasing the turn-on threshold voltage of the ferroelectric FET.
FIG. 3
illustrates one example of a voltage bias applied to source
12
, drain
14
, gate electrode
18
, and substrate
10
in order to produce a polarization within the ferroelectric layer
18
corresponding to a second logic state as is known in the prior art. In this example, +3v is applied to gate electrode
20
, and 0v is applied to source
12
, drain
14
, and substrate
10
. Negative charges are attracted in channel region
16
putting this device in “inversion mode”, thereby creating a potential in channel region
16
equal to the voltage of source
12
and drain
14
, which are biased to 0v. Assuming that the coercive voltage is 3v or less, the electric field thereby created across the ferroelectric will polarize the ferroelectric layer
18
in the direction of that electric field. This electric field will have the effect of decreasing the turn-on threshold voltage of the ferroelectric FET.
FIG. 4
illustrates one example of a voltage bias applied to source
12
, drain
14
, gate electrode
18
, and substrate
10
in order to detect the stored logic state, as is known in the prior art. In this example, +1.5v is applied to gate electrode
20
, 0v is applied to source
12
and substrate
10
, and 0.5v is applied to drain
14
. Assuming that the electric field across ferroelectric layer
18
is less than the coercive voltage, the polarization of ferroelectric
18
is unchanged. A current will flow through source
12
, channel
16
, and drain
14
, the magnitude of which depends on the turn-on voltage of the device. Since the turn-on threshold voltage corresponding to the first logic state is higher than for the second logic state, the magnitude of the current when the first logic state is stored is less than when the second logic state is stored.
When utilized in a memory array, additional transistors providing select functions must generally accompany each ferroelectric FET, thereby increasing the size of the memory array. It would, therefore, be desirable to provide an architecture and bias method of selecting a given ferroelectric FET within an array without requiring additional transistors.
SUMMARY OF THE INVENTION
According to the principles of the present invention, a method of writing a ferroelectric FET having source, drain, gate and substrate terminals and a ferroelectric layer between the gate and the substrate exhibiting hysteresis, forms a polarization in said ferroelectric layer to store first and second logic states such that a selection means is provided when arranged and connected in an array of rows and columns. The array of ferroelectric FETs is arranged in rows and columns, the gate terminal of ferroelectric FETs in the same row coupled to a common word line, the source terminal of ferroelectric FETs in the same row coupled to a common source line, the drain terminal of ferroelectric FETs in the same column coupled to a common bit line, the body terminal of ferroelectric FETs in the same array coupled to a common substrate terminal. A ferroelectric FET is selected for reading and writing within the array by application of bias voltages to the word line, source line, and bit line. To write the ferroelectric FET, a negative voltage whose magnitude is equal to or greater than the coercive voltage is applied to the word line, while ground potential (0v) is applied to the source line, the bit line, and the substra

Affiliated with

Also associated with

Rating

Method of writing ferroelectric field effect transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of writing ferroelectric field effect transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of writing ferroelectric field effect transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3196095