Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-02-13
2004-07-27
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06769106
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a technology capable of reducing resistance in the wiring or capable of improving the process yield by setting a new through-hole in addition to a through-hole for connecting between wires disposed in different layers in a semiconductor integrated circuit having a multi-layer structure, without changing the wiring already set by the conventional method.
BACKGROUND OF THE INVENTION
The number of circuit elements mounted on a semiconductor integrated circuit has been increasing exponentially in recent years. For example, 2.2 million circuit elements are mounted on a one-mega-bit dynamic random access memory (DRAM). The area of a plane that constitutes a circuit is limited. Moreover, the performance of the circuit is controlled by the wiring patterns. Therefore, how to structure the layout of the large number of circuit elements and the wiring for connecting between the circuit elements is an extremely important task. It is not suitable to carry out all the wiring process by hand from the viewpoint of development time and precision. Therefore, the layout of the circuit elements and the wiring patterns are determined automatically on a computer by using the technology of computer aided designing (CAD), as a main practice at present.
FIG. 11
is a schematic view showing a part of a semiconductor integrated circuit having a multi-layer structure that has been wired according to a conventional method.
FIG. 11
is a transmission view of a semiconductor integrated circuit consisting of a first layer and a second layer, looked at from vertically above the circuit surface. The wiring disposed on the first layer and the wiring disposed on the second layer are shown in one plane. The a-wiring
1
, a-wiring
2
, b-wiring
3
, and the c-wiring
4
are the wirings disposed on the first layer. The A-wiring
8
, D-wiring
9
, and the E-wiring
10
are the wirings disposed on the second layer. The a-wiring
1
and
2
, and the A-wiring
8
transmit the same electric signal, and other wirings transmit mutually different electric signals.
An insulation layer is disposed between the first layer and the second layer, thereby to insulate the wirings belonging to one layer from those of the other layer. It is necessary to electrically connect between the a-wiring
1
and the A-wiring
8
, and between the a-wiring
2
and the A-wiring
8
respectively, as these wirings handle the same signal. For this purpose, the a-wiring
1
and the A-wiring
8
are connected to each other via the through-hole
5
, and the a-wiring
2
and the A-wiring
8
are connected to each other via the through-hole
6
. These through-holes are provided to pierce through the insulation layer sandwiched between the first layer and the second layer, in a direction perpendicular to the circuit surface, respectively. Therefore, it is possible to secure electric conduction between the first layer and the second layer through these through-holes. In order to provide these through-holes, according to a conventional automatic wiring, wiring patterns are set subject to a condition that one through-hole is disposed without exception to a pair of these wirings to be connected to each other. Specifically, in the automatic wiring, a setting area is provided on one of the pair of wirings that needs to be electrically connected to each other, and a corresponding area as a projection of the setting area is provided on the other wiring. With this arrangement, a through-hole is set in a shape that pierces through the insulation layer, and the setting area and the corresponding areas are connected to each other.
However, along with the request for making devices smaller in recent years, there has been progress in reduction in the size of a circuit element and a reduction in the width of wiring. As shown in
FIG. 11
, a through-hole is set to have a smaller width than that of wiring. Therefore, a cross-sectional area of one through-hole per circuit surface also becomes smaller, corresponding to the reduction in the wiring width. Further, according to the conventional automatic wiring, only one through-hole for electric conduction is provided for a pair of wirings that are disposed in different layers.
The electric resistance of a through-hole is inversely proportional to cross-sectional area of the through-hole. Therefore, as the reduction in size of a semiconductor integrated circuit has progressed, the resistance of the through-hole has increased, and a current flow has become more difficult.
Further, when a cross-sectional area of a through-hole becomes small, it becomes difficult to form the through-hole by that magnitude, and a probability that a disconnection occurs at the through-hole portion in the process of manufacturing a semiconductor integrated circuit increases. When one through-hole has been disconnected, this semiconductor integrated circuit cannot operate even when there is no problem in other portions of the semiconductor integrated circuit. As a result, this semiconductor integrated circuit cannot be shipped as a product. This leads to a reduction in the production yield of semiconductor integrated circuits.
Further, in general, it has been known that electromigration resistance is lowered in inverse proportion to the square of current density. The current density of a through-hole having a smaller cross-section increases when the same level of current flows. This brings about a problem in that the electromigration resistance is lowered.
In the mean time, in the automatic wiring, it has been known as a countermeasure to increase the number of through-holes to be set in a pair of wirings that are disposed on different layers. For example, when a pair of wirings that have so far been connected to each other through one through-hole are connected to each other through two through-holes, the cross-sectional area of the through-holes on the circuit surface increases by this incremental through-hole portion. Therefore, the resistance decreases by that portion, and other problems can also be prevented. This kind of technique has been disclosed in Japanese Patent Application Laid-open No. 9-62724, Japanese Patent Application Laid-open No. 10-125775, and Japanese Patent Application Laid-open No. 8-306786.
However, as the area of planes that constitute a circuit is limited as described above, it is not advantageous to carry out the automatic wiring subject to a condition that a new area for setting a through-hole is provided. In other words, the area that can be used for the circuit elements and the wiring becomes small by the portion of the increase in the through-hole setting area. This makes it necessary to dispose other wiring by detouring around the area for setting the through-hole, leading to a reduction in the degree of freedom of wiring. As a result, the characteristics of the semiconductor integrated circuit are lowered, and it is not possible to carry out the automatic wiring in the worst case.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of wiring a semiconductor integrated circuit, a semiconductor integrated circuit capable of disposing a new through-hole without changing a wiring pattern after once this wiring pattern has been determined. It is another object of this invention to provide a computer program that contains instructions which when executed on a computer realizes the method according to the present invention on the computer.
The method of wiring according to one aspect of the present invention is a method of wiring a semiconductor integrated circuit, the semiconductor integrated circuit having a first layer and a second layer. The method includes the steps of: disposing a first wiring on the first layer and disposing a second wiring on the second layer, wherein the first and second wirings are disposed subject to a condition that a predetermined number of through-holes are set between the first and second wirings, and the first and second layers being electrically connected to each other; searching for a setting area
Garbowski Leigh M.
Leydig , Voit & Mayer, Ltd.
Renesas Technology Corp.
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