Method of wire bonding for small clearance

Details Method of wire bonding for small clearance Method of wire bonding for small clearance

2000-05-22

2001-11-27

Dunn, Tom (Department: 1725)

Metal fusion bonding

Process

Plural joints

C228S004500, C029S841000, C029S843000, C257S666000

Reexamination Certificate

active

06321976

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of wire bonding for small clearance, and more specifically, to a method of employing a conductive bump over the pad of a chip to prevent a capillary from colliding with the chip during three-dimensional package wiring process.
BACKGROUND OF THE INVENTION
At present, the commercialized electronic products have a trend of being lightweight, thin, short and small size. Therefore, very large scale integrated circuits (VLSI) have been widely used. As the development of semiconductors advances, the total number of transistors in a die greatly increases, and at the same time, the requirement in the density of a package becomes more and more strict. A three dimensional package is thus developed to greatly increase the package density in order to overcome the issue.
However, during packaging, the pad of a chip is soldered to a lead frame by wiring, and when the chips are adhered in a three dimensional manner, a capillary may collide with some higher chips to damage the chips and the capillary because the size of each chip is similar.
In the prior art, the steps of wiring comprises: (
1
) the capillary solders the wire on a pad by a thermal process or super sonic technique; (
2
) the capillary rises to form a vertical wire; (
3
) the capillary translates the wire to the lead frame; and (
4
) another end of the wire is soldered onto the lead frame.
For the process which needs a long wire, a reverse loop D has to be added to the stroke of the capillary to enhance the strength of the wire.
This step is feasible in single chip package wiring. However, in the three dimensional package wiring, the effect of the reverse loop D has to be taken into consideration, as shown in FIG.
1
. The sizes of the upper and lower chips
11
and
12
are almost the same in the package application. Therefore, when the two chips
11
and
12
are assembled together by soldering process, the capillary
14
may collide with the chip
11
to damage the capillary
14
and the chip
11
resulting in failure of wiring if the distance A from the pad
13
in the chip
12
to the rim of the chip
11
is very small and one of the reverse loop D, the radius C of the capillary, and the thickness E of the chip
11
is too big, or the distance A from the center of the pad in the chip
12
to the rim of the chip
11
is too small. The solution of the prior art is to select a smaller capillary
14
. However, there is a disadvantage that the appropriate capillary can not be found if the distance A between the pad
13
in the chip
12
and the rim of the chip
11
is smaller than 0.2 mm.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of wire bonding for small clearance, which overcomes the disadvantage in the prior arts that the distance A between the center of the pad in the chip
12
and the rim of the chip
11
is too small to perform the wiring process by the conventional wiring equipment. The method of the present invention can prevent the capillary from colliding with the chip during the three-dimensional package wiring process. In the present invention, a conductive bump
15
is first formed over the pad
13
of the chip
12
and then the chip is connected to the lead frame by the conventional wiring method. The height H of the bump
15
is determined by the reverse loop D, the radius C of the capillary
14
, the thickness E of the chip
11
, and the distance A between the pad
13
in the chip
12
and the rim of the chip
11
.
Other features and advantages of the invention will become apparent from the following description of the invention that refers to the accompanying drawings.


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