Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-03-18
2003-04-15
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S455000, C438S456000
Reexamination Certificate
active
06548391
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of producing a three-dimensional integrated circuit.
BACKGROUND OF THE INVENTION AND PRIOR ART
Three-dimensional integration means that components produced by means of planar technology are connected vertically. The advantages of a three-dimensionally integrated microelectronic system are e.g. that, in comparison with two-dimensional systems, higher packaging densities and switching speeds can be achieved on the basis of the same design rules. The latter is due to shorter conduction paths between the individual components or circuits on the one hand, and to the possibility of parallel information processing on the other. An optimum increase in the efficiency of the system is achieved, when a connection technology with locally freely selectable vertical contacts, which are suitable for very-large scale integration, is realized.
For producing three-dimensional circuit arrangements with freely selectable vertical contacts, the following methods are known, among others.
In Y. Akasaka, Proc. IEEE 74 (1986) 1703, it is e.g. suggested that polycrystalline silicon should be deposited on a fully processed component layer and that this polycrystalline silicon should be recrystallized so that additional components can be produced in the recrystallized layer. Disadvantages of this method are the yield-reducing degradation of the lower-level components due to the high thermal load during the recrystallization process and the necessarily serial processing of the overall system. The latter causes, on the one hand, comparatively long cycle times in the production process and, on the other hand, it causes a reduction of yield due to the fact that process-dependent outage times add up. Both factors increase the production costs to a substantial extent in comparison with a processing of the individual planes separately from one another in different substrates.
Y. Hayashi et al., Proc. 8
th
lnt. Workshop on Future Electron Devices, 1990, p. 85, additionally discloses that the individual component planes are first produced separately from one another in different substrates. Subsequently, the substrates are thinned, provided with contacts on the front and on the back, and vertically connected by means of a bonding process. This method is advantageous insofar as the vertical integration is finished when the bonding process has been finished, i.e. it is no longer necessary to execute any processing steps at the stacked substrates. The applicability of this method is, however, strongly limited by the circumstance that the substrates must here be thinned down to a few 0.1 &mgr;m (complete removal of the substrate material in the area of the lateral insulating structures), so that this method cannot be used for vertically integrating components which have been produced according to standard semiconductor technologies.
U.S. Pat. No. 4,939,568 describes a method for producing a three-dimensional, integrated circuit structure by stacking individual integrated circuits on a support substrate so as to obtain a stack of individual chips. For this purpose, a substrate with fully processed integrated circuits is first subdivided into individual chips, whereby processing at the wafer level is finished. The chips are tested, and a first individual chip is applied to a support substrate by means of thermocompression. After this step, a further chip is applied to the first chip in the same way. Hence, a first stack of chips is finished before the production of another stack of chips on a further support substrate is started. It follows that further processing of the stacks of chips at the wafer level is not possible by means of this method.
A significant disadvantage of the hitherto mentioned methods results from the fact that the devices available in the field of silicon technology only permit a processing of disk-shaped substrates, the so-called wafers. Substrates other than disk-shaped substrates, especially individual chips, can only be processed in experimental plants, but not within the framework of industrial production with the high yields demanded.
U.S. Pat. No. 5,563,084 describes a method of producing a three-dimensional integrated circuit in the case of which the connection of the individual component planes is established via specially formed via holes. According to this method, two fully processed substrates are connected. Prior to connecting the substrates, the upper substrate is, however, subjected to a functional test by means of which the chips of the substrate that are intact are selected. Subsequently, the substrate is thinned from the back, divided into individual chips and only selected chips that are intact are applied in an aligned, side-by-side mode of arrangement to the lower substrate which is provided with an adhesive layer. This method is, however, disadvantageous insofar as the vertical electric connections between the stacked component planes are realized only subsequently by further processing at the wafer level (wiring). For this purpose, it will, on the one hand, be necessary to use a suitable planarization method, which levels the marked topography of the chip stacks, so that these chip stacks can be processed according to standard disk production processes. On the other hand, the integration density of the final wiring is additionally limited due to the finite positioning accuracy in the chip application process. The lithographic steps executed at the disk level, which are necessary for opening via holes to the metallization plane of the chip applied and for subsequently patterning the final wiring plane, must take into account suitable alignment tolerances so as to be in the “registering range” throughout the whole area of the wafer.
U.S. Pat. No. 5,627,106 additionally discloses a method of three-dimensionally connecting semiconductor components in the case of which semiconductor component structures are produced in and on the upper surface of a first semiconductor substrate. Subsequently, deep trenches are etched into the first semiconductor substrate and filled with a conductive material. Following this, the back of the first semiconductor substrate is ground off and polished so that the trenches filled with conductive material will project. Also the second semiconductor substrate is provided with semiconductor component structures. In addition, connection windows are etched into the second semiconductor substrate, the projecting trenches of the first semiconductor component the projecting trenches of the first semiconductor component being fitted into said windows in a subsequent step. Only after the mechanical connection of the two substrates, are the semiconductor component structures of the first semiconductor substrate connected in an electrically conductive manner to the conductive material in the trenches. A special disadvantage of this method is that the projecting trenches filled with conductive material tend to break off, which makes it more difficult to handle the method in practice.
German patent specification DE 44 33 846 additionally describes a method of producing a vertical integrated circuit structure in the case of which the individual component layers are processed independently of one another in different substrates and joined subsequently. For this purpose, via holes, which extend through all the component layers provided, are first opened at the front of a fully processed top substrate. Following this, a handling substrate is applied and the top substrate is thinned from the back down to the via holes. Finally, a fully processed bottom substrate is connected to the top substrate. After the removal of the handling substrate, the via holes are extended through the remaining layers down to a metallization plane of the bottom substrate, and the electric contact between the top and the bottom substrate is established.
The post-published EP-A-0 926 726 additionally discloses a method of applying diced chips to printed circuit boards. According to this method, the component structures located o
Klumpp Armin
Ramm Peter
Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung
Glenn Michael A.
Glenn Patent Group
Nguyen Thanh
Nguyen Tuan H.
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