Method of verifying design of logic circuit

Details Method of verifying design of logic circuit Method of verifying design of logic circuit

2007-10-24

2010-12-28

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07861197

ABSTRACT:
A method of verifying a design of logic circuit of a semiconductor device having a first circuit block to which the power continuously applied and a second circuit block receiving the power which turns on/off in response to the state of operation modes includes replacing a first basic logic cell including a storage element to a first verification logic cell in the blocks, replacing a second basic logic cell having no storage cell to a second verification logic cell in the blocks, and performing a logical simulation of the device.

REFERENCES:
patent: 7610571 (2009-10-01), Chen
patent: 2007/0245278 (2007-10-01), Chen
patent: 2009/0089725 (2009-04-01), Khan
patent: 2002-259487 (2002-09-01), None

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