Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-08-07
2007-08-07
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10956806
ABSTRACT:
A method of verifying photomask-pattern-correction results includes steps of cutting away photomask patterns of a region to be subjected to correction, forming photoresist models used for execution of an optical-proximity-effect-correction operation, executing the optical-proximity-effect-correction operation of the photomask patterns with respect to the photoresist models, executing an exposure simulation for simulating photoresist patterns formed on a photoresist film to which the photomask patterns are transferred after the optical-proximity-effect-correction operation, and designating parameters required for executions of the cutting away the photomask patterns of the region, the forming of the photoresist models, the optical-proximity-effect-correction operation, and the exposure simulation.
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patent: 6757645 (2004-06-01), Chang et al.
patent: 7003755 (2006-02-01), Pang et al.
patent: 7107571 (2006-09-01), Chang et al.
patent: 11-218899 (1999-08-01), None
patent: 2000-260879 (2000-09-01), None
DLA Piper (US) LLP
Kabushiki Kaisha Toshiba
Siek Vuthe
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