Method of verifying a semiconductor integrated circuit...

Details Method of verifying a semiconductor integrated circuit... Method of verifying a semiconductor integrated circuit...

2005-01-18

2005-01-18

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189050, C365S189070

Reexamination Certificate

active

06845043

ABSTRACT:
A method of verifying a semiconductor integrated circuit apparatus includes (a) providing a semiconductor integrated circuit apparatus including: a first transistor which has a floating gate in which a potential is floated and to which data is written; a second transistor which has a floating gate connected together with the floating gate and reads out the data written to the first transistor; and a control gate unit, which is coupled to the floating gate, controlling an operation of reading out the data of the second transistor; (b) comparing a first data outputted through the second transistor when a first potential is applied to the control gate unit with a second data outputted through the second transistor when a second potential is applied to the control gate unit to generate a comparison result; and (c) verifying the data written to the floating gate based on the comparison result.

REFERENCES:
patent: 6532181 (2003-03-01), Saito et al.
patent: 6538924 (2003-03-01), Dono et al.
patent: 2001-229690 (2001-08-01), None
patent: 2002-025288 (2002-01-01), None
Shukuri, et al., “CMOS Process IE-Flash (Inverse Gate Electrode Flash) Technology for System-on-a Chip”, Oct. 2000.

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