Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-10-19
2003-05-06
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S002000, C703S004000
Reexamination Certificate
active
06560757
ABSTRACT:
The present invention relates to a method of verifying the output from an analogue simulation model of a hardware circuit.
BACKGROUND OF THE INVENTION
In the past during mixed signal IC device or ‘chip’ development, testing departments have had to wait until a device has been reduced to silicon before functional tests can be performed. In view of the increase in the general requirements for mixed signal (using digital and analogue signals) chips and their shrinking product shelf life, the need to reduce development time has risen accordingly. By testing IC device designs prior to reduction to silicon overall development times can be reduced considerably. This means that a device can be brought to market more quickly.
A number of test simulators are known which allow test departments to test how a device will function as soon as a preliminary design is completed. This can be prior to the reduction to silicon of the device.
One type of test simulator is an analog simulator which may be used for non-linear DC, non-linear transient and linear AC analysis. SPICE is an example of an industry standard general-purpose analog circuit simulator. A development of the SPICE simulator is the ELDO simulator which provides the functionality, performance and accuracy of SPICE-level simulation along with improved algorithms which allow more complex circuits to be simulated and also provides a mixed signal simulation capability.
Analog simulators, as the name suggests, allow simulation of a hardware cell being tested at the analog signal level. The simulator provides performance results through the whole range of analog input signals and allows for voltage sweeps. In other words, the cell is tested over a wide range of voltage values, the voltage values being for example applied as inputs. As a result analog simulators provide very accurate descriptions of the designed device operation. However simulation times can be prohibitively protracted especially when a design comprises many thousands or hundreds of thousands of cells to be simulated.
As a solution to the task of describing circuits of such large scale, digital simulators have been developed. Numerous digital simulators have been developed to model the behaviour of circuitry described using a hardware description language (HDL). HDL is a programming language which has been designed and optimised for simulating and thereby describing behaviour of digital circuitry. HDL allows electrical aspects of circuit behaviour to be precisely described. However since only digital signals (which have one of two states) are simulated simulation time scales are much reduced. Additionally, only changes of logic level trigger an evaluation of the effect. A specific example of HDL is the very high speed integrated circuit HDL known as VHDL.
HDL models typically provide a behavioural description of the circuitry of the designed device which can be synthesised into a net list which includes circuit diagrams of the device saved in textual form. In other words, the circuitry of the device is broken down into cells or small circuit portions, each of which has a known behaviour. These cells or small circuit portions are listed in the net list. Operation of the device is simulated by stimulating the net list by the application of a test bench. Test benches are HDL descriptions of circuit stimulus. The outputs of the cell in response to stimulus are compared with expected outputs to verify the behaviour of a circuit over time. The verification results may be analysed to establish how the circuit has functioned.
A problem is that whilst various cells whose operation has an analog type behaviour are modelled as a VHDL behavioural description or a net list of transistors there is no real verification between the cells response in a true analog simulator such as ELDO. As the cells are analogue cells, the analogue simulator would provide a more accurate reflection of the behaviour of the cell. Certainly no such real verification is achieved by automatic means but it is rather a further requirement for the model writer. As such it can be a further source of error in a design. This problem also applies to digital circuits as they can be regarded as analogue cells with very high gains so that the outputs tend to be rail to rail.
VHDL supports many abstract data types which are used to described different signal strengths or commonly used simulation conditions such as unknowns and high-impedance conditions. These non-standard data types have been adopted by the IEEE as standard 1164. Such data types are not applicable to analog simulators which require true analog signals rather than abstract data types.
It is an aim of embodiments of the present invention to at least partly mitigate the above problems.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the present invention there is provided a method of verifying the output from an analogue simulation model of a hardware circuit comprising the steps of stimulating the analogue model by applying a preselected voltage to the or each input pin of the analogue model; driving one or more selected output pins of the analogue model with a test voltage having a selected drive strength different from an expected output drive strength; measuring the output voltage on each output pin; comparing the measured output voltage and the expected output voltage; and responsive to said comparison, providing a verifying output if the measured and expected voltages are not in contradiction.
Preferably, the selected drive strength is weaker than the expected drive strength.
The step of driving one or more selected output pins may comprise the steps of driving the selected output pin of the analogue simulation model with the selected drive voltage which is the voltage of the inverted logic state of the expected voltage on the selected pin.
The method may comprise the steps of reducing the drive strength of the voltage applied to the selected output pin to a weaker drive strength in the voltage of the inverted logic state of the expected voltage on that pin and driving the selected output pins with the weakened voltage.
For one or more output pins where the expected output voltage varies in strength, a test voltage may be selected for the pin having a mid range voltage between the minimum and maximum expected output voltages and, the output pin may be driven with a selected test voltage for that pin at a drive strength which is weaker than the drive strength of the expected output voltage on that pin.
Preferably, the selected output pin(s) on which the expected output voltage is high impedance, the steps of driving selected output pins and measuring the output voltage may comprise the steps of: driving the output pin with a low voltage; measuring the output voltage on the pin; driving the output pin with the high voltage; and measuring the output voltage on the pin.
The analogue model may be a SPICE model, such as an ELDO model.
According to a second aspect of the present invention, there is provided a system for verifying the output from an analogue simulation model of a hardware circuit comprising means for stimulating the analog model by applying a preselected voltage to the or each input pin of the analogue model; means for driving one or more selected output pins of the analog model with the test voltage having a selected drive strength different from an expected output drive strength; means for measuring the output voltage in each output pin; means for comparing the measured output voltage and the expected output voltage; and means for providing a verifying output in response to the comparison if the measured and expected voltages are not in contradiction.
REFERENCES:
patent: 4743842 (1988-05-01), Langone et al.
patent: 4815024 (1989-03-01), Lewis
patent: 5202639 (1993-04-01), McKeon et al.
patent: 5353243 (1994-10-01), Read et al.
patent: 5426770 (1995-06-01), Nuber
patent: 5535223 (1996-07-01), Horstmann et al.
patent: 5682337 (1997-10-01), El-Fishawy et al.
patent: 5822567 (1998-10-01), Takeuchi
patent: 6090152 (2000-07-01)
Liu Andrea
Morris James H.
Skrivanek, Jr. Robert A.
Smith Matthew
STMicroelectronics Limited
LandOfFree
Method of verification does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of verification, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of verification will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3038834