Method of vector generation for estimating performance of...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

07000202

ABSTRACT:
A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. Vectors are generated to estimate integrated circuit performance. The technique accurately estimates of the performance (e.g., transient delays) of an integrated circuit, and has fast execution times. The technique is applicable to small circuits having relatively few transistors, and especially well suited for integrated circuits having millions of transistors and components. The technique handles the effects of deep-submicron integrated circuit technology.

REFERENCES:
patent: 5305229 (1994-04-01), Dhar
patent: 5331568 (1994-07-01), Pixley
patent: 5416721 (1995-05-01), Nishiyama et al.
patent: 5440720 (1995-08-01), Baisuck et al.
patent: 5533148 (1996-07-01), Sayah et al.
patent: 5553008 (1996-09-01), Huang et al.
patent: 5640328 (1997-06-01), Lam
patent: 5655109 (1997-08-01), Hamid
patent: 5706473 (1998-01-01), Yu et al.
patent: 5757655 (1998-05-01), Shih et al.
patent: 6058256 (2000-05-01), Mellen et al.
patent: 6138266 (2000-10-01), Ganesan et al.
patent: 6249898 (2001-06-01), Koh et al.
patent: 404279974 (1992-10-01), None
Appenzeller, David P. et al., “Formal Verification of a PowerPC™ Microprocessor,” Report RC (19971), IBM T.J. Watson Research Center, Yorktown Heights, NY 10598, Mar. 1995, pp. 1-6.
Bryant, R.E., “Algorithmic Aspects of Symbolic Switch Network Analysis,” IEEE Trans. Computer-Aided Design, vol. CAD-6, No. 4, Jul. 1987, pp. 618-633.
Bryant, R.E. et al., “Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis,” 1991 IEEE (CH306-2/91/0000/0350/$01.00), pp. 350-353.
Bryant, R.E., “Graph-Based Algorithms for Boolean Function Manipulation,” IEEE Trans. Comput., vol. C-35, Aug. 1986, pp. 677-691.
Ohlrich, Miles et al., “SubGemini: Identifying SubCircuits Using a Fast Subgraph Isomorphism Algorithm,” 30thACM/IEEE Design Automation Conference, Jan. 1993 (ACM 0-89791-577-1/93/0006-0031 1.50), pp. 31-37.
Shepard, Kenneth et al., “Noise in Deep Submicron Digital Design,” ICCAD '96, 1063-6757/96, 1996 IEEE, 8 pages.

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