Method of using scatterometry measurements to control...

Details Method of using scatterometry measurements to control... Method of using scatterometry measurements to control...

2001-11-08

2004-09-14

Young, Christopher G. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Including control feature responsive to a test or measurement

C356S369000, C356S445000, C356S448000, C382S145000, C382S149000

Reexamination Certificate

active

06790570

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of using scatterometry measurements to control stepper process parameters, and a system for accomplishing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background, an illustrative field effect transistor
10
, as shown in
FIG. 1
, may be formed above a surface
15
of a semiconducting substrate or wafer
11
comprised of doped-silicon. The substrate
11
may be doped with either N-type or P-type dopant materials. The transistor
10
may have a doped polycrystalline silicon (polysilicon) gate electrode
14
formed above a gate insulation layer
16
. The gate electrode
14
and the gate insulation layer
16
may be separated from doped source/drain regions
22
of the transistor
10
by a dielectric sidewall spacer
20
. The source/drain regions
22
for the transistor
10
may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate
11
. Shallow trench isolation regions
18
may be provided to isolate the transistor
10
electrically from neighboring semiconductor devices, such as other transistors (not shown).
The gate electrode
14
has a critical dimension
12
, ie., the width of the gate electrode
14
, that approximately corresponds to the channel length
13
of the device when the transistor
10
is operational. Of course, the critical dimension
12
of the gate electrode
14
is but one example of a feature that must be formed very accurately in modem semiconductor manufacturing operations. Other examples include, but are not limited to, conductive lines, openings in insulating layers to allow subsequent formation of a conductive interconnection, i.e., a conductive line or contact, therein, etc.
In the process of forming integrated circuit devices, millions of transistors, such as the illustrative transistor
10
depicted in
FIG. 1
, are formed above a semiconducting substrate. In general, semiconductor manufacturing operations involve, among other things, the formation of layers of various materials, e.g., polysilicon, insulating materials, etc., and the selective removal of portions of those layers by performing known photolithographic and etching techniques. These processes are continued until such time as the integrated circuit device is complete. Additionally, although not depicted in
FIG. 1
, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate. These conductive interconnections allow electrical signals to propagate between the transistors formed above the substrate.
During the course of fabricating such integrated circuit devices, a variety of features, e.g., gate electrodes, conductive lines, openings in layers of insulating material, etc., are formed to very precisely controlled dimensions. Such dimensions are sometimes referred to as the critical dimension (CD) of the feature. It is very important in modern semiconductor processing that features be formed as accurately as possible due to the reduced size of those features in such modern devices. For example, gate electrodes may now be patterned to a width
12
that is approximately 0.2 &mgr;m (2000 Å), and further reductions are planned in the future. As stated previously, the width
12
of the gate electrode
14
corresponds approximately to the channel length
13
of the transistor
10
when it is operational. Thus, even slight variations in the actual dimension of the feature as fabricated may adversely affect device performance. Thus, there is a great desire for a method that may be used to accurately, reliably and repeatedly form features to their desired critical dimension, i.e., to form the gate electrode
14
to its desired critical dimension
12
.
Photolithography is a process typically employed in semiconductor manufacturing. Photolithography generally involves forming a patterned layer of photoresist above one or more layers of material that are desired to be patterned, and using the patterned photoresist layer as a mask in subsequent etching processes. In general, in photolithography operations, the pattern desired to be formed in the underlying layer or layers of material is initially formed on a reticle. Thereafter, using an appropriate stepper tool and known photolithographic techniques, the image on the reticle is transferred to the layer of photoresist. Then, the layer of photoresist is developed so as to leave in place a patterned layer of photoresist substantially corresponding to the pattern on the reticle. This patterned layer of photoresist is then used as a mask in subsequent etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features or opening-type features, that are to be replicated in an underlying process layer. The features in the patterned layer of photoresist also have a critical dimension, sometimes referred to as a develop inspect critical dimension (DICD).
FIGS. 2 and 3
depict an illustrative embodiment of a wafer
11
that may be subjected to an exposure process in a stepper tool. In general, the stepper exposure process is performed on a stack comprised of one or more process layers or films and a layer of photoresist. For example, as shown in
FIG. 2
, such a stack may be comprised of a layer of polysilicon
36
, formed above the substrate
11
, and a layer of photoresist
38
. Alternatively, an anti-reflective coating (ARC) layer (not shown) may be positioned above the layer of polysilicon
36
and below the layer of photoresist
38
. Of course, such film stacks may be comprised of a vast variety of combinations of process layers and materials.
As shown in
FIG. 3
, a plurality of die
42
are formed above the wafer
11
. The die
42
define the area of the wafer
11
where production integrated circuit devices, e.g., microprocessors, ASIC, memory devices, will be formed. The size, shape and number of die
42
per wafer
11
depend upon the type of device under construction. For example, several hundred die
42
may be formed above an
8
-inch diameter wafer
11
. The wafer
11
may also have an alignment notch
17
that is used to provide relatively rough alignment of the wafer
11
prior to performing certain processes, e.g., an exposure process in a stepper tool.
As shown in
FIG. 2
, the stepper tool contains a representative light source
47
that is used to project light through a reticle (not shown) onto a layer of photoresist
38
. Ultimately, the image in the reticle will be transferred to the layer of photoresist
38
, and the underlying process layer
36
will be patterned using the patterned layer of photoresist
38
as a

Affiliated with

Also associated with

Rating

Method of using scatterometry measurements to control... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of using scatterometry measurements to control..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of using scatterometry measurements to control... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3254728