Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2001-04-25
2002-05-07
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S015000, C438S016000, C356S445000, C356S370000, C356S329000, C356S340000
Reexamination Certificate
active
06383824
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of using scatterometry measurements to control deposition processes. and a system for accomplishing) same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel lengths junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
Typically, integrated circuit devices are comprised of millions of transistors formed above a semiconducting substrate. By way of background, an illustrative field effect transistor
10
, as shown in
FIG. 1
, may be formed above a surface
15
of a semiconducting substrate or wafer
11
comprised of doped-silicon. The substrate
11
may be doped with either N-type or P-type dopant materials. The transistor
10
may have a doped polycrystalline silicon (polysilicon) gate electrode
14
formed above a gate insulation layer
16
. The gate electrode
14
and the gate insulation layer
16
may be separated from doped source/drain regions
22
of the transistor
10
by a dielectric sidewall spacer
20
. The source/drain regions
22
for the transistor
10
may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g. arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate
11
. Shallow trench isolation regions
18
may be provided to isolate the transistor
10
electrically from neighboring semiconductor devices, such as other transistors (not shown). Additionally, although not depicted in
FIG. 1
, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate
11
.
Semiconductor manufacturing generally involves multiple processes whereby multiple layers of material are formed above a semiconducting substrate, and portions of those layers are selectively removed until such time as a completed device is formed. These layers may be patterned using known photolithography and etching techniques. In general, photolithography involves the process of forming a layer of photoresist material above one or more process layers in which a feature, e.g., a metal line, a gate electrode, an opening in a layer of insulating material, will be formed. Thereafter, a pattern that is desired to be transferred into the underlying process layer or layers will be formed in the layer of photoresist material. Then, using one or more etching processes, the underlying process layer is etched using the patterned layer of photoresist as a mask, thereby resulting in a patterned process layer that replicates the pattern formed in the layer of photoresist.
One illustrative process flow for forming a portion of the transistor
10
shown in
FIG. 1
will now be described. Initially, a process layer comprised of a gate insulation material, e.g., silicon dioxide, is formed above the semiconducting substrate
11
. Typically, this is accomplished by an oxidation process. Then, a process layer comprised of a gate electrode material, e.g., polysilicon, is formed above the process layer
17
. The polysilicon layer may be formed by a variety of processes, e.g., by a chemical vapor deposition (“CVD”) process. If desired, an anti-reflective coating layer (not shown) may also be formed above the polysilicon layer to reduce reflections during subsequent photolithography exposure processes. The anti-reflective coating layer may be comprised of a variety of materials, e.g., silicon nitride, silicon oxynitride, etc. Thereafter, a patterned layer (not shown) of photoresist material (positive or negative) is formed above the polysilicon layer using known photolithography techniques, and one or more etching processes will be performed to form a gate electrode structure
14
from the polysilicon layer using the patterned layer of photoresist as a mask.
One problem encountered with existing deposition processes used to form process layers is controlling the thickness of the deposited layer of material. Thickness control of various deposited layers, e.g., silicon dioxide, silicon nitride, silicon oxynitride, polysilicon. metals, etc., is very important in modern semiconductor manufacturing operations. For example, if a layer of insulating material, e.g., silicon dioxide, is made too thin, then conductive metal lines later formed therein may be thinner than anticipated, which may result in an increase in the resistance of the line. As another example, if an insulating layer is made thicker than anticipated by the design process, then subsequent etching processes that may be performed on the insulating layer may have to be performed for a duration that is longer than anticipated to remove the excess material, thereby increasing manufacturing time and reducing manufacturing efficiencies. Previously, the thickness of various deposited layers has been measured by a variety of metrology tools, such as an ellipsometer, a reflectomer, a spectrometer, or some combination thereof These tools tended to work well for measuring flat, uniform thin films, but many modern semiconductor manufacturing processes depend less upon uniform film thickness than surface topography or profile of the process layer. In short, what is desired is a metrology technique and control application that may provide a more robust technique for measurings or determining the topography or surface profile of a process layer, and a method and system for controlling surface planarity using the improved metrology technique and system.
The present invention is directed to a method and system that may solve or at least reduce, some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is directed to a method of using scatterometry measurements to control deposition processes, and a system for accomplishing same. In one embodiment, the method comprises forming at least one grating structure above a substrate, performing a deposition process to form a process layer above the gratings structure, and illuminating the process layer and the grating structure. The method further comprises measuring light reflected off of the process layer and the grating structure after the deposition process is started to generate an optical characteristic trace for the process layer and the grating structure, comparing the generated optical characteristic trace to a target optical characteristic trace that corresponds to a process layer having a desired surface profile, and controlling the deposition process based upon the comparison of the generated trace and the target trace,
REFERENCES:
patent: 5867276 (1999-02-01), McNeil et al.
patent: 5877276 (1999-03-01), Borden
patent: 5880838 (1999-03-01), Marx et al.
patent: 5923423 (1999-07-01), Sawatari et al.
patent: 5955654 (1999-09-01), Stover et al.
patent: 6259521 (2001-07-01), Miller et al.
Advanced Micro Devices , Inc.
Luk Olivia
Niebling John F.
Williams Morgan & Amerson P.C.
LandOfFree
Method of using scatterometry measurements to control... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of using scatterometry measurements to control..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of using scatterometry measurements to control... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2842907