Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Gettering of semiconductor substrate
Reexamination Certificate
1997-09-12
2001-06-26
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Gettering of semiconductor substrate
C438S154000
Reexamination Certificate
active
06251712
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a doping technique in a manufacturing process of an insulated-gate semiconductor device, such as a thin-film transistor (TFT), having a non-single-crystal crystalline silicon film and other semiconductor devices which doping technique minimizes adverse effects on such a device of an impurity (e.g., Ni) contained in the crystalline silicon film. The invention is particularly advantageous when the crystalline silicon film is one that has been formed with the aid of a crystallizing catalyst element (e.g., Ni).
2. Description of the Related Art
In recent years, various studies have been made of insulated-gate semiconductor devices having a thin-film active layer (active region) on an insulative substrate. In particular, a thin-film, insulated-gate transistor, i.e., what is called a thin-film transistor (TFT) has been studied enthusiastically. Thin-film transistors are classified into an amorphous silicon TFT, a crystalline silicon TFT, etc. depending on the material and the crystal state of a semiconductor used. Since “crystalline silicon” mentioned above in non-single-crystal silicon, the above TFTs are generically called non-single-crystal TFTs.
In general, amorphous semiconductors have small electric field mobilities, and therefore cannot be used for a TFT that is required to operate at high speed. Further, P-type amorphous silicon has a very small electric field mobility, which means that amorphous silicon cannot provide a P-channel TFT (PMOS TFT). Therefore, amorphous silicon does not allow formation of a complementary MOS (CMOS) circuit by combining P-channel TFTs and N-channel TFTs (NMOS TFTs).
On the other hand, crystalline semiconductors have larger electric field mobilities than amorphous semiconductors, and hence enable high-speed operation. Since crystalline silicon can provide a PMOS TFT as well as an NMOS TFT, it allows formation of a CMOS circuit.
A non-single-crystal crystalline silicon film can be obtained by thermally annealing, for a long time at a proper temperature (usually more than 600° C.), an amorphous silicon film that has been produced by vapor-phase growth, or by application of strong light such as laser light (optical annealing).
In the thermal annealing method, as described in Japanese Unexamined Patent Publication No. Hei. 6-244104, a crystalline silicon film can be obtained by a thermal annealing process that is shorter and lower in temperature than usual cases by using an effect that an element such as nickel, iron, cobalt, platinum, palladium, or the like (hereinafter called a crystallizing catalyst element or simply a catalyst element) accelerates crystallization of amorphous silicon.
Similar techniques are disclosed in Japanese Unexamined Patent Publication Nos. Hei. 6-318701, 6-333951, etc. It has also been revealed that in a silicon film having such a crystallizing catalyst element, thermal annealing that is lower in temperature than conventional cases enables activation of an impurity element which is performed after impurity regions such as a source and a drain are formed by implanting N-type or P-type impurity ions by ion doping or the like. (Japanese Unexamined Patent Publication Nos. Hei. 6-267980 and Hei. 6-267989)
For the above purpose, it is desired that the concentration of a crystallizing catalyst element be 1×10
15
to 1×10
19
atoms/cm
3
. Crystallization is not accelerated if the concentration is lower than this range, while the characteristics of a silicon semiconductor are impaired if the concentration is higher than this range. It is noted that the concentration of a catalyst element is defined as a maximum of values obtained by an analysis according to the secondary ion mass spectrometry (SIMS). In many cases, a catalyst element is distributed in a film.
Although semiconductor devices produced by using a crystalline silicon film containing a catalyst element for accelerating crystallization have a large electric field mobility, many of those exhibit a large off-current. In particular, where a large number of semiconductor devices are formed on the same substrate, large off-currents, which in itself are undesirable, have a large variation among the semiconductor devices.
Large off-currents and their large variation are believed due to the existence of the catalyst element for accelerating crystallization; that is, mainly due to the fact that the catalyst element exists in junctions.
In particular, the above undesired characteristics are fatal to TFTs that constitute a pixel section of a liquid crystal display.
SUMMARY OF THE INVENTION
Among semiconductor devices produced by using a crystalline silicon film into which nickel was introduced as a catalyst element for accelerating crystallization, those whose impurity regions (sources and drains, etc.) were formed by implanting phosphorus showed relatively low off-currents (about 10 pA or less) with almost no variation. Based on this fact, the inventors have studied properties of phosphorus in detail, and have found a report stating that phosphorus has a feature of gettering impurities.
According to this report, phosphorus shows a particularly high degree of gettering function with respect to nickel. Further, element, such as copper and iron, which are considered to adversely affect semiconductor devices, can be gettered by phosphorus. This leads to an assumption that in the above semiconductor devices, phosphorus neutralizes the properties of nickel in a certain manner, to thereby suppress the adverse effects of nickel on the off-current characteristic.
The invention utilizes the gettering function of phosphorus with respect to nickel. “The gettering function” is defined as an operation that phosphorus captures nickel, thereby reducing the effect of nickel.
For example, a process for manufacturing an n-channel type thin film transistor using the nickel function will be explained as follows.
First, source and drain regions are formed by doping phosphorus ions using a gate electrode as a mask.
A channel region and n-type source and drain regions are formed in an active region of the thin film transistor by the phosphorus ion doping.
After that, thermal annealing or laser annealing is performed. In this process, nickel elements are removed from the channel region that no phosphorus is doped by the function of phosphorus doped in the source and drain regions. That is, the nickel elements are captured by phosphorus and thereby the nickel elements are transferred from the channel region into the source and drain regions.
In the result of the thermal annealing or laser annealing process described above, the nickel elements gather into the source and drain regions. On the other hand, nickel elements are reduced in the region that no phosphorus is doped. The nickel element doped highly in the channel region affects operation of the thin film transistor adversely.
In operation of the thin film transistor, it is required that resistance of the channel region is slightly changed by a voltage applied for the gate electrode. That is, slight change of electric property is needed for the channel region. However, the nickel disturbs the slight change.
Consequently, the Off-current is increased and the characteristics of the thin film transistor fluctuates.
On the other hand, even if nickel is highly doped in the source and drain regions, the off-current is not almost increased and the characteristic does not almost affect.
Accordingly, it is excessively effective for enhancing the characteristic of the thin film transistor to change distribution of nickel in the active region, that is, to increase concentration of nickel in source and drain regions and reduce concentration thereof in the channel region, relatively.
Where a p-channel type film transistor is manufactured, phosphorus ions are doped into the source and drain regions and p-type impurities are doped therein to invert the conductivity type. Thereby, the nickel is transferred into the source and drain regions.
In the invention described abo
Ohnuma Hideto
Tanaka Koichiro
Bowers Charles
Fish & Richardson P.C.
Pert Evan
Semiconductor Energy Laboratory Co,. Ltd.
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