Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2002-04-11
2004-04-13
Pert, Evan (Department: 2829)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Reexamination Certificate
active
06720204
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to bonding pad formation used in integrated circuits, and specifically to an improved method of attaching a Cu wire to a Cu bonding pad.
BACKGROUND OF THE INVENTION
Bond pads are electrically connected to device elements within the semiconductor die structure and provide exposed contact regions of the die permitting electrical connection to components external to the die. Typically, a bonding wire, for example copper, is bonded to the bonding pad at one end and a portion of the lead frame at the other end.
Bonding pads may consist of copper. However, natural oxidation of the copper (Cu) bonding pad surface leads to CuO
2
formation resulting in an undesirable high contact resistance between the Cu wire and Cu metal pad during the bonding process.
U.S. Pat. No. 5,985,765 to Hsiao et al. describes a process to etch the passivation opening over a bonding pad (BP). A capping layer, having a low etch rate, is formed on the bonding pads to prevent their over-etching while fuse openings are etched to the desired depth in the thicker insulating layers.
U.S. Pat. No. 5,824,234 to Jou et al. describes a process of removing fluorine-containing polymers and metal fluoride formed in the etching process from over a bonding pad, reducing the contact resistance.
U.S. Pat. No. 5,559,056 to Weiler describes a method for fabricating bonding pads that utilizes a metal capping layer over a bonding pad that is produced with only two mask and etch steps. The bond pad will withstand ambient temperatures up to approximately 200° C. Weiler describes a capping method and arrangement which prevents corrosion of the metallization layer and prohibits intermetallic growth between the bond pad and the bonding wire.
U.S. Pat. No. 5,719,087 to Chen et al. describes a process protecting a bonding pad from damage by covering the bonding pad with a protective cap of a dielectric material prior to final passivation that protects the bonding pad from a solution suitable to etch contact holes in the final passivation layer.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of attaching a wire to a metal bonding pad that reduces contact resistance.
A further object of the present invention is to provide a method of attaching a copper wire to a copper bonding pad that provides for a stronger contact between the copper wire and the copper bonding pad.
Yet another object of the present invention is to provide a method of attaching a copper wire to a copper bonding pad that provides for better reliability.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor die structure having an exposed metal bonding pad within a chamber is provided. The bonding pad has an upper surface. A hydrogen-plasma is produced within the chamber from a plasma source. The metal bonding pad is pre-cleaned and passivated with the hydrogen-plasma to remove any metal oxide formed on the metal bonding pad upper surface. A wire is then bonded to the passivated metal bonding pad.
REFERENCES:
patent: 5559056 (1996-09-01), Weiler
patent: 5719087 (1998-02-01), Chen et al.
patent: 5824234 (1998-10-01), Jou et al.
patent: 5985765 (1999-11-01), Hsiao et al.
patent: 6320155 (2001-11-01), Barnett
patent: 6355576 (2002-03-01), Haley et al.
patent: 2002/0127825 (2002-09-01), Mui et al.
Nowful et al., “Effects of Plasma Cleaning on the Reliability of Wire Bonding”, Nov. 2001, Advances in Electronic Materia and Packaging, pp. 39-43.*
Wood et al., “Plasma Cleaning of Chip Scale Packages for Improvement of Wire Bond Strength”, Dec. 2000, Internationa Symposium on Electronic Materials and Packaging, pp. 406-408.*
Wolf, Silicon Processing for the VLSI Era vol 2: Process Integration, 1990, 273-276.*
Wolf & Tauber, Silicon Processing for the VLSI Era vol. 1: Process Technology, 1986, pp. 542-547.
Aliyu Yakub
Chooi Simon
Gupta Subhash
Ho Paul Kwok Keung
Roy Sudipto Ranendra
Chartered Semiconductor Manufacturing Ltd.
Pert Evan
Pike Rosemary L. S.
Saile George O.
Stanton Stephen G.
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