Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-08-30
2004-06-08
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06748579
ABSTRACT:
FIELD OF THE INVENTION
The present application relates to the fabrication of semiconductor integrated circuits and, more particularly, to a method of using a filler or “dummy” metal for aiding in subsequent design changes.
BACKGROUND OF THE INVENTION
Semiconductor integrated circuits are designed and fabricated by first preparing a schematic diagram or hardware description language (HDL) specification of a logical circuit in which functional elements are interconnected to form a particular logical function. With standard cell technology, for example, a schematic diagram or HDL specification is synthesized into standard cells of a specific cell library. A series of computer-aided design tools generate a netlist of the selected cells and the interconnections between the cells. The netlist is used by a floor planner or placement tool to place the selected cells at particular locations in an integrated circuit layout pattern. The interconnections between the cells are then routed along predetermined routing layers. Once the selected cells have been placed and routed, the netlist, the cell layout definitions, the placement data and the routing data together form an integrated circuit layout definition which is used to fabricate the integrated circuit.
The integrated circuit is fabricated by depositing multiple layers on a substrate known as a wafer. The lowest, “base” layers include the active areas of the transistors, including the diffusion regions and the gate oxide areas, and the desired patterns of the polysilicon gate electrodes. These layers are fabricated through a sequence of pattern definition steps, which are interspersed with other processed steps such as oxidation, etching, doping and material deposition. The additive or subtractive process steps are preceded by masking steps, which define the desired geometric patterns on the wafer. One or more layers are then deposited on top of the base layers and patterned to form conductive segments, which interconnect the various semiconductor devices formed in the base layers. Electrical contacts or vias are formed to electrically connect a conductive segment on one of the metal layers with a conductive segment or semiconductor device on one of the other layers on the wafer.
There is often a desire to release semiconductor designs to fabrication as early as possible in the design cycle. Subsequent design verification often results in the identification of design errors. Correction of the design errors may involve the addition of one or more standard cells into the netlist and/or changes or additions to the placement and routing data. Unfortunately, correction of these design errors can be extremely costly if made during the fabrication process. Correction may involve re-cutting the base layer mask set, re-cutting the metal layer mask set and, if wafer fabrication has begun, scrapping entire wafer lots.
Methods are therefore desired that allow for changes in the interconnections or “nets” between the cells without necessarily requiring the fabrication of a full metal layer mask set.
SUMMARY OF THE INVENTION
One embodiment of the present invention is directed to a method of fabricating photolithography masks for an integrated circuit. The method includes fabricating a set of routing layer masks, which define conductive segments including signal segments, power supply segments and filler segments on various routing layers of the integrated circuit. The filler segments are located in areas unused by the signal segments and the power supply segments. A first via mask is fabricated, which defines electrical connections between the conductive segments on at least two of the routing layers, including connections between the filler segments on one of the layers and the power supply segments on another of the layers. If a signal net on the integrated circuit needs changing after fabricating at least one of the routing layer masks and the first via mask, a second via mask is fabricated to replace the first via mask. The second via mask decouples a first of the filler segments from a first of the power supply segments and couples the first filler segment into the signal net.
Another embodiment of the present invention is directed to a method for fabricating an integrated circuit having a logical function. The method includes fabricating first and second routing layer masks and a first via mask. The first routing layer mask includes power supply segments and signal segments. The second routing layer mask includes signal segments and filler segments, wherein the filler segments are located in unused areas of the second routing layer mask. The first via mask defines vias that electrically couple the filler segments to the power supply segments. If the logical function is changed after the masks have been fabricated, a second via mask is fabricated. The second via mask decouples a filler segment from the power supply segments and couples the filler segment to a signal segment defined by the first routing layer mask to implement the logical function change. The integrated circuit is then fabricated with the first and second routing layer masks and the second via mask.
Yet another embodiment of the present invention is directed to a collection of masks for fabricating a portion of an integrated circuit. The collection of masks includes first and second routing layer masks and first and second via masks. The first routing layer mask defines conductive segments, including a plurality of signal segments and at least one power supply segment. The second routing layer mask defines conductive segments, including a plurality of signal segments and at least one filler segment located in an area unused by the signal segments. The first via mask defines locations of conductive vias between the conductive segments defined by the first and second routing layer masks, including a first via that couples the filler segment to the power supply segment. The second via mask is a replacement for the first via mask. The second via mask eliminates the first via and adds a second via that couples the filler segment to one of the signal segments defined by the first routing layer mask instead of the power supply segment.
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Dillon Michael N.
Khakzadi Khosro
Peterson Scott A.
Levin Naum
LSI Logic Corporation
Siek Vuthe
Westman Champlin & Kelly
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