Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-06-06
2003-02-04
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S672000, C438S735000
Reexamination Certificate
active
06514874
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuits and to methods of manufacturing integrated circuits. More particularly, the present invention relates to a method of using controlled resist footing on silicon nitride substrate for smaller spacing of integrated circuit device features.
BACKGROUND OF THE INVENTION
Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to put millions of devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC.
One limitation to the smallness of IC critical dimensions is conventional lithography. In general, projection lithography refers to processes for transferring patterns between various media. According to conventional projection lithography, a silicon slice, the wafer, is coated uniformly with a lithographic coating. The lithographic coating is a radiation-sensitive film or coating (photoresist).
An exposing source of radiation (such as light, x-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the mask, containing a particular pattern. The radiation-sensitive coating is generally suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern.
The image area becomes selectively crosslinked and consequently either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble (i.e., uncrosslinked) or deprotected areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
Projection lithography is a powerful and essential tool for microelectronics processing. As feature sizes are driven smaller and smaller, optical systems are approaching their limits caused by the wavelengths of the optical radiation.
One alternative to projection lithography is EUV lithography. EUV lithography reduces feature size of circuit elements by lithographically imaging them with radiation of a shorter wavelength. “Long” or “soft” x-rays (a.k.a, extreme ultraviolet (EUV)), wavelength range of lambda=50 to 700 angstroms are used in an effort to achieve smaller desired feature sizes.
In EUV lithography, EUV radiation can be projected onto a resonant-reflective reticle. The resonant-reflective reticle reflects a substantial portion of the EUV radiation which carries an IC pattern formed on the reticle to an all resonant-reflective imaging system (e.g., series of high precision mirrors). A demagnified image of the reticle pattern is projected onto a resist coated wafer. The entire reticle pattern is exposed onto the wafer by synchronously scanning the mask and the wafer (i.e., a step-and-scan exposure).
Although EUV lithography provides substantial advantages with respect to achieving high resolution patterning, errors may still result from the EUV lithography process. For instance, the reflective reticle employed in the EUV lithographic process is not completely reflective and consequently will absorb some of the EUV radiation. The absorbed EUV radiation results in heating of the reticle. As the reticle increases in temperature, mechanical distortion of the reticle may result due to thermal expansion of the reticle.
Both conventional projection and EUV lithographic processes are limited in their ability to print small features, such as, contacts, trenches, polysilicon lines or gate structures. As such, the critical dimensions of IC device features, and, thus, IC devices, are limited in how small they can be.
Conventional lithography can utilize photoresist materials and anti-reflective coating (ARC) materials to pattern geometric shapes on an integrated circuit. One problem with the use of photoresist and ARC layers is interfacial layer formation. Interfacial layer formation refers to a situation where the components of the photoresist and the ARC become mixed in a narrow zone between the two layers leading to resist footing. “Resist footing” refers to the presence of a small protrusion at the bottom of the resist feature after development. Generally, convention IC designers consider resist footing to complicate line width determination and reduce critical dimension control.
Thus, there is a need to pattern IC devices using non-conventional lithographic techniques. Further, there is a need to form smaller feature sizes, such as, smaller trench lines. Yet further, there is a need for a method of using controlled resist footing on silicon nitride substrate for smaller spacing of integrated circuit device features.
SUMMARY OF THE INVENTION
An exemplary embodiment is related to a method of fabricating an integrated circuit. This method can include providing a layer of silicon nitride over a semiconductor substrate where the layer of silicon nitride has a first thickness selected based on a desired size of extensions; providing a layer of photoresist material over the layer of silicon nitride; patterning the layer of photoresist to form photoresist features being separated at the top of the photoresist features by one minimum lithographic feature; and etching a portion of the layer of silicon nitride to form a hole for an integrated circuit device feature. The photoresist features include extensions at the bottom of the photoresist features. The extensions define footings which reduce the separation at the bottom of the photoresist features. As such, exposed portions of the layer of silicon nitride are less than one minimum lithographic feature in width.
Briefly, another exemplary embodiment is related to a method of forming an integrated circuit device feature. This method can include providing a silicon nitride layer having a thickness selected based on a desired size of extensions; and forming photoresist features over the silicon nitride layer. The photoresist features include extensions and provide a mask for etching the silicon nitride layer at a width which is smaller than one minimum lithographic feature.
Briefly, another embodiment is related to an integrated circuit. This integrated circuit is manufactured by a method that includes providing a layer of silicon nitride over a semiconductor substrate where the layer of silicon nitride has a first thickness selected based on a desired size of extensions; providing a layer of photoresist material over the layer of silicon nitride; patterning the layer of photoresist to form photoresist features being separated at the top of the photoresist features by one minimum lithographic feature; and etching a portion of the layer of silicon nitride to form a hole for an integrated circuit device feature. The photoresist features include extensions at the bottom of the photoresist features. The extensions define footings which reduce the separation at the bottom of the photoresist features. As such, exposed portions of the layer of silicon nitride are less than one minimum lithographic feature in width.
Other principle features and advantages of the present invention will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims.
REFERENCES:
patent: 5989979 (1999-11-01), Liu et al.
patent: 6174816 (2001-01-01), Yin et al.
Hui Angela T.
Singh Bhanwar
Yu James Jiahua
Advanced Micro Devices , Inc.
Cuneo Kamand
Foley & Lardner
Kilday Lisa
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