Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-08-22
2006-08-22
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07096438
ABSTRACT:
A method for determining validity of a proposed loop iteration schedule comprising the steps of receiving a dependence graph including operations and edges between said operations; receiving a performance specification; receiving an assignment of latencies to operations of said dependence graph; and determining existence of a placement of clock cycle-boundaries in said dependence graph such that all dependence and timing constraints are satisfied for the performance specification.
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Gupta Shail Aditya
Sivaraman Mukund
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