Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-11-27
2007-11-27
Ellis, Kevin L. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
10897348
ABSTRACT:
The present invention provides a method of updating the cache state information for store transactions in an system in which store transactions only read the cache state information upon entering the unit pipe or store portion of the store/load queue. In this invention, store transactions in the unit pipe and queue are checked whenever a cache line is modified, and their cache state information updated as necessary. When the modification is an invalidate, the check tests that the two share the same physical addressable location. When the modification is a validate, the check tests that the two involve the same data cache line.
REFERENCES:
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patent: 2002/0188817 (2002-12-01), Norden et al.
patent: 2003/0225980 (2003-12-01), Henry et al.
patent: 2005/0138295 (2005-06-01), Hammarlund et al.
Barrick Brian David
Hicks Dwain Alan
Osanai Takeki
Carr LLP
Ellis Kevin L.
International Business Machines - Corporation
Rifai D'Ann N.
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