Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1995-12-01
1999-03-30
Dang, Trung
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438427, 438430, 438431, 438426, H09L 2176
Patent
active
058888810
ABSTRACT:
A process for fabricating a recessed field oxide area comprises providing a substrate having isolation stacks and first and second recesses having openings therein, the first recesses being wider than the second recesses. The recesses can have a depth in the approximate range of 200.ANG.-3000.ANG.. Next, the first and second recesses are lined with nitride, and the substrate is blanketed with a conformal material which bridges the openings of the second recesses but not the openings of the first recesses. The conformal material and the nitride is removed from horizontal surfaces of the isolation stacks, and essentially all of the conformal material is removed from the first recesses. At least a portion of the conformal material is left in the second recesses. Subsequent to the step of removing the conformal material, the substrate and the conformal material is oxidized to create field oxide areas at the first and second recesses.
REFERENCES:
patent: 4495025 (1985-01-01), Haskell
patent: 4541167 (1985-09-01), Havemann
patent: 4868136 (1989-09-01), Ravaglia
patent: 4892614 (1990-01-01), Chapman et al.
patent: 4916087 (1990-04-01), Takeoka et al.
patent: 4980311 (1990-12-01), Namose
patent: 5087586 (1992-02-01), Chan et al.
patent: 5130268 (1992-07-01), Liou et al.
patent: 5175122 (1992-12-01), Wang et al.
patent: 5342480 (1994-08-01), Nisihzawa et al.
patent: 5366925 (1994-11-01), Lur et al.
patent: 5382541 (1995-01-01), Bajor et al.
patent: 5438016 (1995-08-01), Figura et al.
patent: 5472904 (1995-12-01), Figura et al.
Ghandi, "VLSI Fabrication Principles", 1983, pp. 479-482 and pp. 495-497.
Toshiyuki Nishihara et al., "A 0.5um Isolation Technology Using Advanced Poly Silicon Pad LOCOS (APPL)", IEEE, 1988, PP. 100-103.
H.S. Yang et al., "Poly Void Formation in Poly Buffer LOCOS Process", Extended Abstracts of the Spring electrochemical Society Meeting, 1992, p. 442.
J.M. Sung, "The Iimpact of Poly-removal Techniques on Thin Thermal Oxide Property in Poly-Buffered LOCOS Technology", IEEE Transactions on Electron Devices, Aug. 9, 1991, pp. 1970-1973.
Stanley Wolf, "A Review of IC Isolation Technologies--Part 6", Solid State Technology, Dec. 19922, pp. 39-41.
R.L. Guldi, "Characterication of Poly-Buffered LOCOS in Manufacturing Environment", J. Electrochem. Soc., Dec. 1989, pp. 3815-3820.
Tin-Hwang Lin, "Twin-White-Ribbon Effect and Pit Formationo Mechanism in PBLOCOS", J. Electrochem. Soc., Jul. 1991, pp. 2145-2149.
N. Ghezzo, "LOPOS: Adavanced Device Isolation for a 0.8um CMOS/BULK Process Technology", Journal of th Electrochemical Society, Jul. 1989, pp. 1992-1996.
N. Shimizu et al., "A Poly-Buffere Recessed LOCOS Process for 256Mbit DRAM Cells", IEEE, IEDM 92-279, pp. 10.6.1-10.6.4.
Park et al., "A Novel LOCOS-Type Isolation Technology Free of the Field Oxide Thinning Effect", Extended Abstracts of the 1993 International Conference of Solid State Devices and Materials, Makuhari, 1993, pp. 528-530.
IBM Technical Disclosure Bulletin, Vol 29, No. 2, 7/1986.
Figura Thomas
Jeng Nanseng
Dang Trung
Micro)n Technology, Inc.
LandOfFree
Method of trench isolation during the formation of a semiconduct does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of trench isolation during the formation of a semiconduct, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of trench isolation during the formation of a semiconduct will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1214419