Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
1998-10-19
2001-09-11
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S788000, C438S935000, C438S790000
Reexamination Certificate
active
06287989
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for treating a semiconductor wafer and in particular, but not exclusively, to what is known as planarisation.
2. Description of the Related Art
It is common practice in the semi-conductor industry to lay down layers of insulating material between conducting layers in order to prevent short circuits. If a layer of insulating material is simply deposited in the normal way undulations begin to build up as the layers pass over the metallic conductors which they are designed to insulate. Various techniques have been developed to try to overcome this problem by filling the trenches or valleys between the conductors to a height above the top of the conductors so that after treatment a generally planar layer exists on the top of the wafer. One example of such a technique is to spin on layers of polyimide to smooth out the surfaces. However, in practice, narrow trenches tend to be incompletely filled whilst wide valleys are not fully leveled. As the 2-D dimensions of devices are reduced, these problems are accentuated.
SUMMARY OF THE INVENTION
One aspect the invention resides in a method of treating a semi-conductor wafer comprising, depositing a liquid short-chain polymer having the general formula Si
x
(OH)
y
or Si
x
H
y
(OH)
z
on the wafer to form a generally planar layer.
The reference to the polymer being liquid is simply intended to indicate that it is neither gaseous nor solidified at the moment of deposition.
Another aspect the invention resides in a method of treating a semi-conductor wafer in a chamber including, introducing into the chamber a silicon-containing gas or vapour and a compound, containing peroxide bonding, in vapour form, reacting the silicon-containing gas or vapour with the compound to form a short-chain polymers on the wafer to form a generally planar layer.
The silicon-containing gas or vapour may be inorganic and preferably is silane or a higher silane, which may be introduced into the chamber with an inert carrier gas, for example nitrogen. The compound may be, for example, hydrogen peroxide or ethandiol.
The method may further comprise removing water and/or OH from the layer. For example the layer may be exposed to a reduced pressure and/or exposed to a low power density plasma, which may heat the layer to 40 to 120° C.
The method may further comprise forming or depositing an under layer prior to the deposition of the polymer. This under layer may be silicon dioxide and may have a thickness of between 1000 and 3000 Å. It may for example be 2000 Å thick. The under layer may conveniently be deposited by plasma enhanced chemically vapour deposition. Either the under layer and/or the wafer may be pretreated by, for example a plasma, to remove contaminants. In that case it may be pretreated with a plasma, for example using oxygen as a reactive gas.
Similarly the surface of the deposited polymer layer may be treated in a plasma using a reactive oxygen gas in order to enhance chain lengthening and cross-linking within the polymer. This gas could be, for example, oxygen, nitrogen or hydrogen peroxide vapour and other gases may be appropriate. The plasma has a heating effect which enhances crosslinking, but there may also be a radiation effect from the various gases. This chain linking may alternatively be catalysed by exposing the polymer layer to UV light, x-rays or ion bombardment. However, in many applications acceleration of chain linking may not be desirable; instead it may be desirable for the polymer molecule particles to settle before significant chain linking occurs.
The method may further comprise depositing or forming a capping layer on the surface of the deposited layer. This capping layer may be silicon dioxide. The capping layer is deposited after a proportion of the condensation reactions have occurred and water has been removed from the layer.
The method may further comprise heating the polymer layer and this heating preferably takes place after capping. The polymer layer may be heated to between 180-220° C. for between 50-70 minutes. For example it may be heated to 220° C. for 60 minutes. The layer may subsequently be allowed to cool to an ambient temperature and then reheated to 430-470° C. for 30-50 minutes. For example the second heating may last 40 minutes at 450° C. Indeed this second heating may suffice and may be achieved using a furnace, heat lamps, a hotplate or plasma heating.
In one preferred arrangement the polymer layer may be heated to between 200-450° C., prior to capping, in order that the cap can be deposited at elevated temperatures. Although the capping layer could be deposited in one or more steps e.g. a ‘cold’ capping layer deposited at the temperature of the planarising layer followed by a hot capping layer; the polymer layer having first been heated to 200-450° C. as described above.
The density of the hydrogen peroxide may be in the range of 1.20-1.35 gms/cc and a density of 1.25 gms/cc may be particularly preferred. The hydrogen peroxide is preferably at 50% concentration when introduced into the chamber.
The ambient temperature within the chamber may be within the range of 0-80° C. during the deposition of the polymer layer, but the wafer platten is preferably at 0° C. or at the dew point of the polymer when in vapour form. Low pressure is also desirable but requires low temperatures (eg 400 mT, −10° C.).
In order to avoid heating the platten, the wafer is preferably lifted from the platten for each processing step which involves heating.
The method can be used to achieve planarisation or gap filling. In the latter case the ambient chamber temperature may conveniently be even higher.
The invention also includes wafers treated by any of the methods set out above and semi-conductor devices including polymer layers formed by the method above.
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Bowers Charles
Jones Volentine PLLC
Nguyen Thanh
Trikon Technologies Limited
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